H04L7/06

Estimating clock phase error based on channel conditions

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

Estimating clock phase error based on channel conditions

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

Transmission device, reception device, communication system, signal transmission method, signal reception method, and communication method

A transmission device of the disclosure includes: a clock signal transmitting circuit that outputs a clock signal onto a clock signal line; a data signal transmitting circuit that outputs a data signal onto a data signal line; and a blanking controller that controls the clock signal transmitting circuit to output a predetermined blanking signal, in place of the clock signal, from the clock signal transmitting circuit to the clock signal line in synchronization with a blanking period of the data signal.

Amplitude caching in receive from many communications networks

In various examples there is a communications network comprising a plurality of nodes connected via an interconnection medium to form a receive-from-many communications network. The network has a synchronisation mechanism which synchronizes a signal frequency of the nodes. The network has at least one store holding signal amplitude data of signals previously sent between specified pairs of nodes of the communications network. An amplitude controller uses the stored data to adjust amplitudes of signals communicated between at least one of the pairs of nodes of the communications network.

Amplitude caching in receive from many communications networks

In various examples there is a communications network comprising a plurality of nodes connected via an interconnection medium to form a receive-from-many communications network. The network has a synchronisation mechanism which synchronizes a signal frequency of the nodes. The network has at least one store holding signal amplitude data of signals previously sent between specified pairs of nodes of the communications network. An amplitude controller uses the stored data to adjust amplitudes of signals communicated between at least one of the pairs of nodes of the communications network.

Transmission apparatus and receiving apparatus
10951327 · 2021-03-16 · ·

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

One-line synchronous interface

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

One-line synchronous interface

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

CHANNEL TRAINING USING A REPLICA LANE

Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

CHANNEL TRAINING USING A REPLICA LANE

Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.