A receiving apparatus is provided, including: a receiving unit to receive a plurality of pulses including a synchronization pulse and a data pulse having a data pulse width corresponding to a data value; a searching unit to search for pulse information indicating a pulse period or the like that falls within a synchronization pulse acceptable range from among pulse information indicating pulse periods or pulse widths of the respective pulses; a detecting unit to detect whether pulse information of a second pulse at a predetermined location relative to a first pulse corresponding to the searched pulse information indicates a pulse period or the like that falls within a data pulse acceptable range; an identifying unit to identify the first pulse as the synchronization pulse on condition that the pulse information of the second pulse indicates a pulse period or the like that falls within the data pulse acceptable range.

A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.

A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.

Certain aspects of the present disclosure provide techniques for radar detection by an apparatus. In certain aspects a method for radar detection by an apparatus includes selecting one or more radar transmission parameters based on a reference time, wherein the reference time is common to at least a group of vehicles. The method further includes performing radar detection using the selected radar transmission parameters and the reference time.

Certain aspects of the present disclosure provide techniques for radar detection by an apparatus. In certain aspects a method for radar detection by an apparatus includes selecting one or more radar transmission parameters based on a reference time, wherein the reference time is common to at least a group of vehicles. The method further includes performing radar detection using the selected radar transmission parameters and the reference time.

A processing unit processes an input signal from an external apparatus and includes a first terminal to which a reference voltage is input from the external apparatus, a second terminal to which a first pulse signal having a first frequency is input from the external apparatus, and a control portion to process the input signal. A memory stores data to be transmitted to the external apparatus, and a clock generating unit generates a clock signal having a higher frequency than the first frequency of the first pulse signal. To transmit a data signal to the external apparatus from the processing unit, the control portion switches a load between the first terminal and the second terminal based on the data stored in the memory during a period in which a second pulse signal having a second frequency lower than the first frequency is input from the external apparatus.

A processing unit processes an input signal from an external apparatus and includes a first terminal to which a reference voltage is input from the external apparatus, a second terminal to which a first pulse signal having a first frequency is input from the external apparatus, and a control portion to process the input signal. A memory stores data to be transmitted to the external apparatus, and a clock generating unit generates a clock signal having a higher frequency than the first frequency of the first pulse signal. To transmit a data signal to the external apparatus from the processing unit, the control portion switches a load between the first terminal and the second terminal based on the data stored in the memory during a period in which a second pulse signal having a second frequency lower than the first frequency is input from the external apparatus.

A frame delimiter detection system and method includes a phase differentiator and buffering module, a phase-to-I/Q reformatting module, a dot product module, an I/Q-to-polar reformatting module, a dot product comparison module, and a frame delimiter detection module. The method may include receiving in-phase and quadrature-phase (I/Q) formatted frequency domain input samples configured as a frame delimiter in a communication packet. An I/Q formatted dot product may be generated from the I/Q formatted frequency domain input samples and a reference pattern indicative of an expected frame delimiter. Further, a frame delimiter detection signal may be generated based on a magnitude of the I/Q formatted dot product.

A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).

A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit (564, 565) configured to: receive a modulated embedded master-slave clock signal (584) that comprises a system clock signal (582) with an embedded frame start signal (580); demodulate the modulated embedded master-slave clock signal (584); and re-create therefrom the system clock signal (588, 585) and the frame start signal (590, 586).