A system for compensating wire characteristics includes a transmission pre-emphasis module of a transmission transceiver that sends high level pre-emphasis training bits and low level pre-emphasis training bits along a wired connection, a reception pre-emphasis module of a receiver that receives the high level pre-emphasis training bits and low level pre-emphasis training bits along the wired connection, a pre-emphasis analysis module of the receiver that analyzes the high level pre-emphasis training bits and low level pre-emphasis training bits to determine a pre-emphasis level. The system further includes a controller that interfaces with the transmission transceiver and the receiver, the controller communicates the pre-emphasis level to the transmission transceiver.

A system for compensating wire characteristics includes a transmission pre-emphasis module of a transmission transceiver that sends high level pre-emphasis training bits and low level pre-emphasis training bits along a wired connection, a reception pre-emphasis module of a receiver that receives the high level pre-emphasis training bits and low level pre-emphasis training bits along the wired connection, a pre-emphasis analysis module of the receiver that analyzes the high level pre-emphasis training bits and low level pre-emphasis training bits to determine a pre-emphasis level. The system further includes a controller that interfaces with the transmission transceiver and the receiver, the controller communicates the pre-emphasis level to the transmission transceiver.

A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

A frame synchronization system (1) according to this invention includes a frame signal generation circuit (20) configured to generate a frame signal including a plurality of first frame signals each including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed from at least one symbol and is set with an average amplitude lower than an average amplitude of the first payload signal, and a frame synchronization circuit (60) configured to receive the frame signal via an optical transmission path (70), and detect the first frame synchronization signal from a received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, coordinate values, on an IQ plane, of the signals at identical symbol positions of the plurality of divided frames are added over the plurality of frames, and a symbol specified by magnitude comparison in the frame based on an addition result is determined as the first frame synchronization signal. Even if a transmission rate is high, it is possible to decrease the probability of erroneous synchronization, thereby shortening the time until frame synchronization is established.

A frame synchronization system (1) according to this invention includes a frame signal generation circuit (20) configured to generate a frame signal including a plurality of first frame signals each including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed from at least one symbol and is set with an average amplitude lower than an average amplitude of the first payload signal, and a frame synchronization circuit (60) configured to receive the frame signal via an optical transmission path (70), and detect the first frame synchronization signal from a received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, coordinate values, on an IQ plane, of the signals at identical symbol positions of the plurality of divided frames are added over the plurality of frames, and a symbol specified by magnitude comparison in the frame based on an addition result is determined as the first frame synchronization signal. Even if a transmission rate is high, it is possible to decrease the probability of erroneous synchronization, thereby shortening the time until frame synchronization is established.

The present application relates to control systems, clock synchronization methods, controllers, node devices, and vehicles. In one example control system provided in this application, a primary controller directly sends a reference clock signal to at least one node device by using a ring network, and the at least one node device performs timing based on a frequency of the reference clock signal. The reference clock signal is obtained by performing frequency division on a local clock signal of the primary controller.

A phase-shifter circuit arranged to receive a reference timing signal and to output a phase-shifted form of the reference timing signal. The phase-shifter circuit comprises a delay circuit arranged to receive the reference timing signal and a delay control signal, and to delay transitions within the reference timing signal to generate the phase-shifted form of the reference timing signal, wherein the amount of delay applied by the delay circuit to the transitions within the reference timing signal is controllable by the delay control signal. The phase-shifter circuit further comprises a delay control circuit arranged to receive a re-timed signal comprising transitions re-timed to transitions of the phase-shifted form of the reference timing signal output by the phase-shifter circuit, and to generate the delay control signal for the delay circuit based on the received re-timed signal.

A phase-shifter circuit arranged to receive a reference timing signal and to output a phase-shifted form of the reference timing signal. The phase-shifter circuit comprises a delay circuit arranged to receive the reference timing signal and a delay control signal, and to delay transitions within the reference timing signal to generate the phase-shifted form of the reference timing signal, wherein the amount of delay applied by the delay circuit to the transitions within the reference timing signal is controllable by the delay control signal. The phase-shifter circuit further comprises a delay control circuit arranged to receive a re-timed signal comprising transitions re-timed to transitions of the phase-shifted form of the reference timing signal output by the phase-shifter circuit, and to generate the delay control signal for the delay circuit based on the received re-timed signal.

An electronic controller of a restraint control system for a vehicle comprises an electronic control unit including a first serial interface. The electronic controller also comprises a communications controller including a second serial interface and a plurality of PSI5 (Peripheral Sensor Interface 5) digital communications interfaces. Each of the first and second serial interfaces are Serial Peripheral Interfaces (SPI) in direct communications with one another, and the digital communications interfaces are each configured to communicate with a remote sensor. The communications controller is configured to transmit a voltage sync pulse to each of the remote sensors via the PSI5 digital communications interfaces in response to a synchronization command received from the electronic control unit via the serial interconnection. The voltage sync pulses on each of the PSI5 interfaces may be staggered and non-overlapping to reduce EMI production and to reduce the current load of the electronic controller.