Disclosed are a time synchronization method, a time synchronization device, a time synchronization apparatus and a storage medium. The method includes: periodically generating, by a local device, a synchronization request signal, and determining a first reference ID of the local device; sending the synchronization request signal and the first reference ID to peer devices; receiving a second reference ID and time information sent from each peer device through a communication link; and updating time of the local device according to the time information transmitted from a calibration link, the calibration link being a corresponding communication link of a target reference ID in second reference IDs sent from the peer devices.

A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

In one embodiment, methods for monitoring devices within a network by a controller are described. The method may include receiving a first request from a first device to authenticate a role of the first device as a grandmaster in a precision time protocol (PTP). Additionally, the method may include granting the first request designating the role of the first device as the grandmaster. The method may further include receiving a second request from a second device to authenticate that a clock announce message is from an authorized grandmaster. Additionally, the method may include determining whether the first device is authorized to send the clock announce message to the second device and, based on the determining, sending a message granting or denying permission for the first device to sync with the second device.

In one embodiment, methods for monitoring devices within a network by a controller are described. The method may include receiving a first request from a first device to authenticate a role of the first device as a grandmaster in a precision time protocol (PTP). Additionally, the method may include granting the first request designating the role of the first device as the grandmaster. The method may further include receiving a second request from a second device to authenticate that a clock announce message is from an authorized grandmaster. Additionally, the method may include determining whether the first device is authorized to send the clock announce message to the second device and, based on the determining, sending a message granting or denying permission for the first device to sync with the second device.

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

A method and a device for providing a global clock in a system, the terminals in the system are channel connected to each other via paths, each terminal is communicatively connected to a clock source ultimately via a signal recording unit, respectively, the clock source sends a calibration signal to the network, the signal recording unit records the current transmitting time T (0) of the calibration signal, each terminal will receive the calibration signal sequentially due to different distances from the clock source and will return the signal, the backward signals are returned to the signal recording unit along the network sequentially, and the signal recording unit records the time T (n) of each backward signal sequentially, in this way, the signal recording unit can then measure the delay between each terminal and the clock source signal, which can be used as a correction parameter to ensure that all terminals are in exactly the same time reference, in addition, in this way, there is no need to control the length of the clock cables from each terminal to the clock source, and no special consideration is required for clock routing, and difficulties in system assembly, calibration, maintenance and expansion brought by large amounts of cable are avoided.

A system and method of effecting time synchronization between disparate nodes on a network where at least one node has knowledge of the true network time, at least one other node requires synchronization to the true network time, and a third node is utilized to facilitate the synchronization process.

A method and a structure for determining a global clock among systems are disclosed. When a standardized time reference is required among systems, a reference clock source may transmit a calibration signal, and a transmitting time T.sub.d (0) may be recorded. Each system may respectively record an arrival time T.sub.a (n), transmit a return signal to a signal recording unit of the reference clock source, and record a transmitting time T.sub.b (n), after receiving the calibration signal. Similarly, because of different distances, the signal recording unit may record arrival times T.sub.d (n) of the return signals subsequently, and determine time delays Delay (n) between systems and the reference clock source respectively. When all the systems are required to have a completely standardized time reference, a corresponding Delay (n) may be acquired and transmitted to each system. Each system may determine zero deviations T.sub.c (n) of various local clocks from the reference clock source, and take T.sub.c (n) as a correction parameter to correct its own system clock, so that the local clocks of all the systems have a completely standardized time reference.

A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.