Hardware masking may be used as a countermeasure to make power analysis attacks more difficult. Masking attempts to decouple the secret and/or processed values of a cryptographic algorithm from its intermediate values. One method of masking probabilistically splits each bit of a computation into multiple shares. Mask-share domains (i.e., the wires and gates that perform a computation on a share) are physically spaced to reduce coupling between mask-share domains. The mask-share domains may be connected to the same power supply network. The physical distance between mask-share domains along the power-supply network may be selected to reduce coupling between mask-share domains that may occur via the power supply network. The mask-share domains may each be connected to different on-chip power supply networks.

One or more keys are derived from a master key by executing a plurality of encryption operations. A first encryption operation uses the master key to encrypt a plaintext input having a plurality of bytes. Multiple intermediate encryption operations are performed using a respective intermediate key generated by a previous encryption operation to encrypt respective plaintext inputs having a number of bytes. At least two bytes of a plaintext input have values based on a respective set of bits of a plurality of sets of bits of an initialization vector, wherein individual bits of the respective set of bits are introduced into respective individual bytes of the plaintext input and the respective set of bits has at least two bits and at most a number of bits equal to the number of bytes of the plaintext input.

An integrated circuit device includes a semiconductor substrate layer and at least one active layer including electronic components and supported by the semiconductor substrate layer. The semiconductor substrate layer and the at least one active layer are sandwiched between two protective layers acting as physical obstacles to prevent the passage of radiations. In addition, the two protective layers are electrically connected to a detection circuit that can monitor an electrical information of the protective layers and detect a physical attack of at least one of the two protective layers, based on the monitored electrical information.

This application relates to a synchronization circuit for synchronizing signals used in a threshold implementation operation process performing in an S-box of an encryption circuit. In one aspect, the synchronization circuit includes an enable signal generator configured to generate an enable signal. The synchronization circuit may also include a synchronization unit included in an encryption circuit and located inside an S-box that performs a threshold implementation operation that calculates by dividing bits of an input signal into bits equal to or greater than the number of bits of the input signal. The synchronization unit may be configured to synchronize signals used in a threshold implementation operation process based on the generated enable signal.

Systems and methods for protecting block cipher computation operations from external monitoring attacks. An example apparatus for implementing a block cipher may comprise a memory device to store instructions for computing a block cipher; and a processing device coupled to the memory device. The processing device performs a Data Encryption Standard (DES) cryptographic operation with multiple rounds of a Feistel structure, each round including a substitution function and a transformation function that combines an expansion function and a permutation function into a single operation. The transformation function transforms a first input portion of an internal state of the respective round and a second input portion of the internal state into a first output portion and a second output portion of data. The second output portion is equal to the first input portion and the first output portion is dependent on a combined permutation output from the transformation function.

The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.

A cipher accelerator is provided. An encryption and decryption circuit is configured to perform an encryption and decryption operation according to a control signal. The encryption and decryption operation includes a plurality of normal rounds and a plurality of redundant rounds. A controller is configured to provide a control signal to the encryption and decryption circuit according to a first variable value and a second variable value. The encryption and decryption circuit is configured to divide the normal rounds into a first normal section and a second normal section according to the first variable value, and divide the redundant rounds into a first redundant section and a second redundant section according to the second variable value. The encryption and decryption circuit is configured to perform the first normal section, the first redundant section, the second normal section, and the second redundant section sequentially.

A host processing device instructs a plurality of data processing (DP) accelerators to configure themselves for secure communications. The host device generates an adjacency table of each of the plurality of DP accelerators. Then the host device then establishes a session key communication with each DP accelerator and sends the DP accelerator a list of other DP accelerators that the DP accelerator is to establish a session key with, for secure communications between the DP accelerators. The DP accelerator establishes a different session key for each pair of the plurality of DP accelerators. When all DP accelerators have established a session key for communication with other DP accelerators, according to the respective list of other DP accelerators sent by the host device, then the host device can assign work tasks for performance by a plurality of DP accelerators, each communicating over a separately secured communication channel.

This disclosure relates to, among other things, electronic device security systems and methods. Certain embodiments disclosed herein provide for protection of cryptographic keys and/or associated operations using both an operating system security service and a software-based whitebox cryptographic security service executing on a device. Leveraging operating system security services and software-based whitebox cryptographic security services may provide enhanced security when compared to using either service alone to protect cryptographic keys and associated operations. In additional embodiments, server-side cryptographic security solutions may be further used to enhance device security implementations.

An apparatus and system for remote attestation of a power delivery network is disclosed. Embodiments of the disclosure enable remote attestation of the power delivery network by storing a trusted golden reference waveform in secure memory. The trusted golden reference waveform characterizes a power delivery network in response to a load generated on the power delivery network. A remote cloud server generates a server-generated remote attestation of the power delivery network by receiving an attestation packet from the power delivery network and verifying whether the attestation packet is consistent with an expected power delivery network identity.