A cryptographic device (100) arranged to compute a target block cipher (B.sub.t) on an input message (110), the device comprising a first and second block cipher unit (121, 122) arranged to compute the target block cipher (B.sub.t) on the input message, and a first control unit (130) arranged to take the first block cipher result and the second block cipher result as input, and to produces the first block cipher result only if the block cipher results are equal.

An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

Methods, systems, and apparatuses for defending against cryptographic attacks using clock period randomization. The methods, systems, and apparatuses are designed to make side channel attacks and fault injection attacks more difficult by using a clock with a variable period during a cryptographic operation. In an example embodiment, a clock period randomizer includes a fixed delay generator and a variable delay generator, wherein a variable delay generated by the variable delay generator is based on a random or pseudorandom value that is changed occasionally or periodically. The methods, systems, and apparatuses are useful in hardware security applications where fault injection and/or side channel attacks are of concern.

Systems, methods, and apparatuses can protecting a secret on a device with limited memory, while still providing tamper resistance. To achieve the lower memory usage, embodiments can apply a memory-hard function MHF to the secret S to obtain a result Y, which can be used in an encoding process to obtain a code C. After applying the MHF, a prove function can generate a proof value that is used in a decoding (e.g., a verification of computation process) of the code C. The code C can include the proof value, the secret S, and the result Y, and can be sent to a decoding device that verifies the code C as part of a decoding process.

A detection circuit of electromagnetic fault injection includes: a shielding layer configured to shield interference; at least one group of metal-oxide semiconductor MOS transistors, where a source end of the at least one group of MOS transistors is connected to the shielding layer; at least one latch, where a drain end of the at least one group of MOS transistors is connected to an input end of the at least one latch; and a signal output module, where an input end of the signal output module is connected to an output end of the at least one latch. The detection circuit could detect in real time and alarm electromagnetic fault injection in time to ensure robustness and safety of a chip.

A security chip includes: a first dielectric layer; a second dielectric layer disposed on the first dielectric layer, where the first dielectric layer is an optically denser medium relative to the second dielectric layer, and a roughness of an upper surface of the first dielectric layer is greater than or equal to a preset threshold, so that light entering the second dielectric layer from the first dielectric layer is able to be totally reflected and/or scattered; and a semiconductor chip disposed on the second dielectric layer. Based on the above technical solution, light incident from a lower surface of the first dielectric layer is able to be totally reflected or scattered by the upper surface of the first dielectric layer, so that most of light cannot reach a logic or storage area on the front of the security chip, thereby achieving the purpose of resisting a laser attack.

An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.

There is provided a device of protecting an Integrated Circuit from perturbation attacks. The device includes a sensing unit configured to detect a perturbation attack, the sensing unit comprising a set of digital sensors comprising at least two sensors, the sensors being arranged in parallel. Each digital sensor provides a digitized bit output having a binary value, in response to input data, the sensing unit being configured to deliver at least one binary vector comprising a multi-bit value, the multi-bit value comprising at least two bit outputs provided by the set of digital sensors. The sensing device further comprising an analysis unit, the analysis unit being configured to receive at least one binary vector provided by the sensing unit, the analysis unit being configured to detect a perturbation attack from the at least one binary vector.

A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.

A system and method for storing and accessing password verification data on multi-user computer systems that prevents remote attacks. Along with commonly-employed measures that limit the number of unsuccessful attempts to login or otherwise verify a password, it allows users to choose relatively simple passwords with full security. The secret component cannot be easily leaked or exfiltrated does not require periodic backup and is isolated in a way that allows it to be protected by conventional security measures such as safes, alarm systems and video surveillance from attackers who somehow gain access to the computing facility.