A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive n.sup.th root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

Example implementations provide machine readable storage storing machine executable instructions, arranged, when processed by a processor, for a succeeding generation player device accessing an unassigned share in a secret the instructions comprising C instructions to: (a.) receive an intermediate generation share of a set of intermediate shares, the intermediate generation share being arranged to facilitate access to the unassigned share and the intermediate generation share having been derived by an intermediate generation player device from shares of further shares provided by a set of preceding generation player devices; (b.) receive, from a set of other intermediate generation player devices, a set of other intermediate generation shares of the set of intermediate shares, to facilitate access by the succeeding generation player device to the unassigned share in conjunction with the intermediate generation share; and (c.) access the unassigned share using the intermediate generation share and the set of other intermediate generation shares.

Improvements to post-quantum lattice-based digital signature schemes are disclosed. By sampling cryptographic material, including cryptographic key matrices and masking vectors from a uniform distribution, embodiments eliminate the need for a security check during generation of a digital signature vector. As a result, digital signatures can be generated faster and at a lower failure rate. A generating device can generate a verification matrix A and a secret matrix S from a uniform distribution, and an error matrix E from a special distribution (such as a Gaussian). The generating device can combine the three matrices to generate a public matrix Y. The first and the fourth matrices (A, Y) can be used as a public key used to verify digital signatures. The second and the third matrices (S, E) can be used as a private key used to generate digital signatures.

An apparatus and method with homomorphic encryption are included. An apparatus includes a processor configured to, and/or coupled with a memory storing instructions to configure the processor to: generate, from a ciphertext corresponding to a polynomial having a first degree for performing a homomorphic encryption operation, split polynomials having a second degree by factorizing the polynomial, wherein the split polynomials have a second degree that is less than the first degree, generate partial operation results by performing an element-wise operation using the split polynomials, and generate a homomorphic encryption operation result corresponding to the ciphertext by joining the partial operation results.

Polynomial multiplication for side-channel protection in cryptography is described. An example of an apparatus includes one or more processors to process data; a memory to store data; and polynomial multiplier circuitry to multiply a first polynomial by a second polynomial, the first polynomial and the second polynomial each including a plurality of coefficients, the polynomial multiplier circuitry including a set of multiplier circuitry, wherein the polynomial multiplier circuitry is to select a first coefficient of the first polynomial for processing, and multiply the first coefficient of the first polynomial by all of the plurality of coefficients of the second polynomial in parallel using the set of multiplier circuits.

A homomorphic encryption processing device includes the processing circuitry is configured to generate ciphertext operation level information based on field information. The field information represents a technology field to which homomorphic encryption processing is applied. The ciphertext operation level information represents a maximum number of multiplication operations between homomorphic ciphertexts without a bootstrapping process. The processing circuitry is further configured to select and output a homomorphic encryption parameter based on the ciphertext operation level information. The processing circuitry is further configured to perform one of a homomorphic encryption, a homomorphic decryption and a homomorphic operation, based on the homomorphic encryption parameter. The homomorphic encryption processing device may adaptively generate a homomorphic encryption parameter according to a ciphertext operation level information determined based on a field information, and may perform a homomorphic encryption, a homomorphic decryption and a homomorphic operation based on the homomorphic encryption parameter.

A method may include obtaining a set of multivariate quadratic polynomials associated with a multivariate quadratic problem and generating an Ising Model connection weight matrix “W” and an Ising Model bias vector “b” based on the multivariate quadratic polynomials. The method may also include providing the matrix “W” and the vector “b” to an annealing system configured to solve problems written according to the Ising Model and obtaining an output from the annealing system that represents a set of integers. The method may also include using the set of integers as a solution to the multivariate quadratic problem.

A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of F.sub.p.sup.2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

Systems, apparatuses, methods, and computer program products are disclosed for post-quantum cryptography (PQC). An example method includes transmitting a first portion of an electronic communication to a client device over a non-PQC communications channel. The example method further includes transmitting a second portion of the electronic communication to the client device over a PQC communications channel. In some instances, the first portion of the electronic communication may comprise overhead data, and the second portion of the electronic communication may comprise payload data.

Bitcoins and the underlying blockchain technology are one of the main innovations in building decentralized applications. The effects of quantum computing on this technology are analyzed in general. Provided herein are effective solutions to address security vulnerabilities in a blockchain-based system that can be exploited by a quantum attacker.