H04L12/44

MULTIDROP MAKE AND BREAK SYSTEM

A multidrop system configured to be installed within a motor control center (MCC) of an industrial automation system includes a trunkline. The trunkline includes multiple multidrop make and break devices connected through a trunkline cable. Each of the multidrop make and break device includes a first network component, and a second network component. The first network component is configured to form a first subnet over the trunkline. The second network component is configured to couple a MCC withdrawable unit and form a second subnet over a branchline that connects one or more nodes within the MCC withdrawable unit. The multidrop make and break device is configured to couple the MCC withdrawable unit to, and decouple the MCC withdrawable unit from, the second network component without disrupting the first subnet.

Mapping of virtual routing and forwarding (VRF) instances using ethernet virtual private network (EVPN) instances
11575541 · 2023-02-07 · ·

Methods, systems, and devices map an arbitrary number of Virtual Routing and Forwarding (VRF) instances to an Ethernet Virtual Private Network (EVPN) instance (EVI) of a leaf and spine network. For example, a spine network device executes a primary EVI to provide an EVPN to a plurality of leaf network devices, each leaf network device executing a secondary EVI to provide a plurality of network virtualization overlays to tenants of the network. The primary EVI is associated with a primary VRF instance, and each secondary EVI of the plurality of secondary EVIs is associated with a secondary VRF instance of a plurality of secondary VRF instances. The spine network device defines mappings between routes within the primary VRF instance and routes within each secondary VRF instance. The spine network device translates, based on the one or more mappings, network traffic between the primary EVI and the plurality of secondary EVIs.

Fractal tree structure-based data transmit device and method, control device, and intelligent chip

The present invention provides a fractal tree structure-based data transmit device and method, a control device, and an intelligent chip. The device comprises: a central node that is as a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; the plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data; the central node, the forwarder modules and the plurality of leaf nodes are connected in the fractal tree network structure, and the central node is directly connected to M the forwarder modules and/or leaf nodes, any the forwarder module is directly connected to M the next level forwarder modules and/or leaf nodes.

Fractal tree structure-based data transmit device and method, control device, and intelligent chip

The present invention provides a fractal tree structure-based data transmit device and method, a control device, and an intelligent chip. The device comprises: a central node that is as a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; the plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data; the central node, the forwarder modules and the plurality of leaf nodes are connected in the fractal tree network structure, and the central node is directly connected to M the forwarder modules and/or leaf nodes, any the forwarder module is directly connected to M the next level forwarder modules and/or leaf nodes.

SECURE ETHERNET AND TRANSMISSION CONTROL PROTOCOL

Methods and systems are provided for providing secure Ethernet transmissions. In some aspects, an autonomous vehicle system is provided and can include a first system-on-chip being configured to provide data to a second system-on-chip via an Ethernet harness, a first switch being configured to: receive the data from the first system-on-chip, and provide the data to a first transceiver for transmission to the second system-on-chip, the first switch being configured to provide first transmission data to the first transceiver and to prohibit receipt of retrieval data from the second system-on-chip, and the first transceiver configured to communicate with the second system-on-chip via the Ethernet harness.

SECURE ETHERNET AND TRANSMISSION CONTROL PROTOCOL

Methods and systems are provided for providing secure Ethernet transmissions. In some aspects, an autonomous vehicle system is provided and can include a first system-on-chip being configured to provide data to a second system-on-chip via an Ethernet harness, a first switch being configured to: receive the data from the first system-on-chip, and provide the data to a first transceiver for transmission to the second system-on-chip, the first switch being configured to provide first transmission data to the first transceiver and to prohibit receipt of retrieval data from the second system-on-chip, and the first transceiver configured to communicate with the second system-on-chip via the Ethernet harness.

Barrier synchronization system and parallel information processing apparatus

A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.

Barrier synchronization system and parallel information processing apparatus

A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.

Interconnection network with adaptable router lines for chiplet-based manycore architecture

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

Interconnection network with adaptable router lines for chiplet-based manycore architecture

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.