Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.

In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

A master module (52A) mediates communication between an electric apparatus (6) to which a signal processing device (100) is connected and apparatus control devices (3, 4B) that control the electric apparatus. The master module is provided with: a plurality of first communication ports (54) for respectively connecting to a plurality of signal processing devices via a communication cable (51) for transmitting a superimposed signal; a data signal processing unit (44) that extracts a data signal from the superimposed signal received through the first communication port; an abnormality information generation unit (504) that, on the basis of status information that is included in the extracted data signal and indicates an abnormal state of the electric apparatus, generates abnormality information which indicates information related to an abnormality that has occurred; and an information output unit (503) that outputs the abnormality information such that the apparatus control devices can acquire the abnormality information.

A single ended receiver includes a current mode logic circuit, a differential to single amplifier, and a voltage detector. The current mode logic circuit is configured to receive an input signal and a reference voltage value and is configured to output a first output signal. The differential to single amplifier is coupled to the current mode logic circuit and is configured to receive the first output signal and to output a second output signal. The voltage detector is coupled to the differential to single amplifier and is configured to output a control signal to the differential to single amplifier according to the reference voltage value. The differential to single amplifier is further configured to adjust a voltage value of the differential to single amplifier internal signal according to the control signal, so that a duty cycle of the second output signal is adjusted.

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

A device for a serial bus system. The device has a receiver receiving a signal from a bus of the bus system. For a message exchanged between user stations of the bus system, a recessive bus state is overwritable by a dominant bus state and the recessive bus state is generated differently in the first communication phase than in the second communication phase. The receiver generates a digital signal based on the received signal, and the signal being output to a communication control unit for evaluating the data contained in the digital signal. The receiver uses a first and second reception threshold for generating the digital signal in the second communication phase, the second reception threshold having a voltage value lower than that of the first reception threshold or higher than the highest voltage value which, during normal operation, is established on the bus for a dominant bus.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.