In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Aspects of the subject disclosure may include, receiving a communication signal, and generating an electromagnetic wave that propagates along an outer surface of a dielectric layer environmentally formed on a cable. The dielectric layer can be a liquid disposed on an outer surface of the cable that enables the electromagnetic wave to propagate along the dielectric layer of the cable without an electrical return path, and conveys the communication signal. Other embodiments are disclosed.

Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

A transmitting device of the present disclosure include: a first driver that includes a first sub-driver unit which operates on a basis of a first control signal and a second sub-driver unit which operates on a basis of, of the first control signal and a second control signal, a signal selected through a first selecting operation, and is configured to be able to set a voltage at a first output terminal; and a controller that controls the first selecting operation.

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A power line communication device including a current path provided between a first terminal and a second terminal. A coupling circuit includes a first circuit of a first inductor connected in parallel with a first capacitor and a first resistor, wherein the coupling circuit is connected between the first and second terminals. A sensor is configured to sense a communication parameter of the coupling circuit. The communication parameter may be a resonance of the first circuit, the quality (Q) factor of the resonance, the bandwidth (BW) of the coupling circuit, the resistance of the first resistor, or the impedance of the first circuit. A transceiver is adapted to couple to the first and second terminal to transmit a signal onto the current path or receive a signal from the current path responsive to the parameter of the coupling circuit and a level of current in the current path sensed by the sensor.

A half-duplex communication system includes a first half-duplex transceiver. The first half-duplex transceiver includes a first microprocessor and a current sensor connected to an input of the microprocessor, and the half-duplex transceiver is coupled to a first and second voltage source. The first voltage source is at a first voltage level and the second voltage source is at a second voltage level. The first microprocessor is configured to transmit data by alternatively connecting the first voltage source and the second voltage source to a conductor and to receive data in the form of pulses of current on the conductor detected by said current sensor.