A system for receiving multipath signals is disclosed. The system includes an equalizer that includes an input for a received data signal, wherein the received data comprises a first multipath component and a second multipath component. The equalizer further includes a channel impulse response estimator coupled to the input configured to determine one or more channel impulse response (CIR) estimates for the first multipath component and the second multipath component. The equalizer further includes a statistical estimation module coupled to the channel impulse response estimator configured to estimate a state of the first multipath component and the second multipath component based on the one or more channel impulse response estimates. The equalizer further includes a detector coupled to the statistical estimation module configured to detect data from the received data signal based on an estimated future state of the first multipath component and the second multipath component.

A method for equalizer correction in a communication network includes (a) obtaining raw equalizer coefficients in a frequency domain, (b) removing time delay from the raw equalizer coefficients to generate corrected equalizer coefficients in a time domain such that a direct current (DC) corrected equalizer coefficient of the corrected equalizer coefficients has a phase of zero, and (c) converting the corrected equalizer coefficients from the time domain to the frequency domain.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

an orthogonal frequency division multiplexed (OFDM) output signal produced by a device in response to an OFDM input signal is accessed. The OFDM input signal includes OFDM input symbols in the time domain and the OFDM output signal includes OFDM output symbols in the time domain. The OFDM output symbols are time-aligned to the OFDM input symbols and a phase of the OFDM output signal is de-rotated with respect to the OFDM input signal. A complex equalization filter is applied to the OFDM output symbols in the time domain to obtain an estimate of the OFDM input symbols A distortion signal of the OFDM output signal is determined by subtracting the estimate of the OFDM input symbols. An error vector magnitude (EVM) is determined by dividing a root mean square of the distortion, by a root mean square of the OFDM input signal.

A communication quality estimating device estimates an error rate of a signal with FEC capable of correcting K errors. The device obtains a frequency measurement value that indicates a frequency at which a codeword including m errors is received. The device determines a transition probability and a continuation probability included in each of a plurality of formulae, such that a frequency calculation value that is calculated using the plurality of formulae and indicates a frequency at which a codeword including m errors is received is brought close to the frequency measurement value. The device calculates a frequency at which a codeword including more than K errors is received, by using the plurality of formulae each with the determined transition probability and the determined continuation probability. The device estimates after-FEC error rate based on a result of the calculation.

A communication quality estimating device estimates an error rate of a signal with FEC capable of correcting K errors. The device obtains a frequency measurement value that indicates a frequency at which a codeword including m errors is received. The device determines a transition probability and a continuation probability included in each of a plurality of formulae, such that a frequency calculation value that is calculated using the plurality of formulae and indicates a frequency at which a codeword including m errors is received is brought close to the frequency measurement value. The device calculates a frequency at which a codeword including more than K errors is received, by using the plurality of formulae each with the determined transition probability and the determined continuation probability. The device estimates after-FEC error rate based on a result of the calculation.

Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.