A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

An apparatus of user equipment (UE) includes a radio integrated circuit (IC), an adjustable external low noise amplifier (eLNA) external to the radio IC, and processing circuitry. The radio IC includes a receive signal circuit path including an adjustable gain internal low noise amplifier (iLNA), and a transmit signal circuit path including a digital-to-analog converter (DAC) circuit configured to convert digital signals to analog baseband signals for transmitting. The processing circuitry is configured to provide digital values of the digital signals to the DAC circuit and initiate adjusting gain of one or both of the iLNA and the eLNA according to the digital values.

An apparatus of user equipment (UE) includes a radio integrated circuit (IC), an adjustable external low noise amplifier (eLNA) external to the radio IC, and processing circuitry. The radio IC includes a receive signal circuit path including an adjustable gain internal low noise amplifier (iLNA), and a transmit signal circuit path including a digital-to-analog converter (DAC) circuit configured to convert digital signals to analog baseband signals for transmitting. The processing circuitry is configured to provide digital values of the digital signals to the DAC circuit and initiate adjusting gain of one or both of the iLNA and the eLNA according to the digital values.

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

A data communication method in which input digital data is received and encoded into an encoded waveform having zero crossings representative of the input digital data. The encoding includes generating the encoded waveform based upon a continuous piecewise function having sinusoidal components. The continuous piecewise function may be used in generating a plurality of symbol waveforms, each of which occupies a period of the encoded waveform and represents bits of the input digital data. The plurality of symbol waveforms are defined so that a value of a phase offset used in the continuous piecewise function is different for each of the plurality of symbol waveforms, thereby resulting in each symbol waveform having a different zero crossing. An encoded analog waveform is generated from a representation of the encoded waveform and transmitted to a receiver.

A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

A reception device includes: a receiver that receives a multiplexed signal; a first demapper that demaps the multiplexed signal, with a second modulated symbol stream of a second data series being included in the multiplexed signal as an undefined signal component, to generate a first bit likelihood stream of a first data series; a second demapper that demaps the multiplexed signal, with a first modulated symbol stream of the first data series being included in the multiplexed signal as an undefined signal component, to generate a second bit likelihood stream of the second data series; a first decoder that performs error control decoding on the first bit likelihood stream to derive the first data series; and a second decoder that performs error control decoding on the second bit likelihood stream to derive the second data series.

A waveform shaping circuit is configured without including a diode that is affected by temperature. The waveform shaping circuit includes: a capacitor with one end into which a differential signal Vd0 is inputted and another end connected to an output; an impedance element that has one end connected to the other end of the capacitor and another end into which a target constant voltage is applied; a switch circuit that is constructed of a series circuit with an impedance element and a switch without including a diode, has one end connected to the output, and has another end into which the target constant voltage is applied; and a switch control circuit that shifts the switch into an on state during a low voltage period in an AC component of the differential signal and shifts the switch to an off state during a high voltage period of the AC component.

A waveform shaping circuit is configured without including a diode that is affected by temperature. The waveform shaping circuit includes: a capacitor with one end into which a differential signal Vd0 is inputted and another end connected to an output; an impedance element that has one end connected to the other end of the capacitor and another end into which a target constant voltage is applied; a switch circuit that is constructed of a series circuit with an impedance element and a switch without including a diode, has one end connected to the output, and has another end into which the target constant voltage is applied; and a switch control circuit that shifts the switch into an on state during a low voltage period in an AC component of the differential signal and shifts the switch to an off state during a high voltage period of the AC component.

An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.