Provided is a method of estimating a Direct Current (DC) offset in an Ultra-Low Power (ULP) receiver. The method includes receiving a signal from an output of an Analog to Digital Converter (ADC) in the ULP receiver. The signal includes a correlated variable DC component for at least one of an in-phase arm and a quadrature arm of the ULP receiver. The method also includes estimating a DC offset compensation parameter in a plurality of phases for a plurality of stages based on the received signal such that the estimating includes calculating the DC offset compensation parameter in a magnitude estimation phase for the plurality of stages and calculating the DC offset compensation parameter in a sign estimation phase for the plurality of stages.

A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.

A spectrally efficient multi-carrier communication apparatus with advanced features of carrier management. The apparatus is flexible to changes in the form of the sub-carrier and their location in frequency. This invention can use non-standard pulses at arbitrary frequencies providing a greater control of the carrier. The additional features can be used for spectral efficiency, to correct signal distortion or for privacy. Also disclosed is a novel multiplexing method that saves spectrum called Spectral Shape Division Multiplexing (SSDM), preferred embodiments of the transmitter and receiver. Two complementary algorithms help the invention excel among other existent methods. The disclosed algorithms can similarly be adapted to other systems. A correction method for spectrally efficiency is calibrated to all desired noise levels for maximum benefit. An iterative multi-carrier reduction method dramatically reduces the error on overlapped subcarriers.

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

Methods and systems for channel estimation using iterative channel tracking algorithm, in a communication system combined multiple input multiple output (MIMO) technology with orthogonal frequency division multiplexing (OFDM), are disclose. The initial channel estimation of a data packet uses the first preamble inserted in front of the OFDM blocks. After demodulating subsequent one or more OFDM blocks, iterative channel tracking method is used for channel estimation until the next preamble is received. The iterative channel tracking is based on the received signals and the demodulated results of subsequent one or more OFDM blocks.

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.