Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

A differential signal receiver is provided. The differential signal receiver includes a first differential difference amplifier, a second differential difference amplifier, a latch and a first inverter. The first differential difference amplifier and the second differential difference amplifier compare a voltage value of an input signal with a first threshold value and a second threshold value, respectively, so as to output a first difference signal and a second difference signal, respectively. The second threshold value is an opposite value of the first threshold value. The latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal. The first inverter is configured to receive the first latch signal and output the first output signal. The first output signal has a duty cycle being the same as a duty cycle of the input signal.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

A transceiver device for a bus system and a method for reducing conducted emissions. The transceiver device has a transmitting stage for transmitting a transmit signal to a first bus wire of a bus of the bus system, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and for transmitting the transmit signal to a second bus wire of the bus, a receiving stage for receiving the bus signal transmitted on the bus wires, and an emission reduction unit for controlling a switch-on path of a first stand-off device in the transmitting stage as a function of whether or not a dominant stage of the transmit signal occurs.

A transceiver device for a bus system and a method for reducing conducted emissions. The transceiver device has a transmitting stage for transmitting a transmit signal to a first bus wire of a bus of the bus system, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and for transmitting the transmit signal to a second bus wire of the bus, a receiving stage for receiving the bus signal transmitted on the bus wires, and an emission reduction unit for controlling a switch-on path of a first stand-off device in the transmitting stage as a function of whether or not a dominant stage of the transmit signal occurs.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

An apparatus and digital signal processing means are disclosed for excision of co-channel interference from signals received in crowded or hostile environments using spatial/polarization diverse arrays, which reliably and rapidly identifies communication signals with transmitted features that are self-coherent over known framing intervals due to known attributes of the communication network, and exploits those features to develop diversity combining weights that substantively excise that co-channel interference from those communication signals, based on differing diversity signature, timing offset, and carrier offset between the network signals and the co-channel interferers. In one embodiment, the co-channel interference excision is performed in an appliqué that can be implemented without coordination with a network transceiver.