Patent classifications
H04L25/14
High speed data links with low-latency retimer
This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. The data link is initiated with the full data path and a first sequence of data packets is transferred via the full data path in accordance with a low data rate setting. While transferring the first sequence of data packets, the first sequence of data packets is manipulated in the full data path to establish a connection of the data link, and in response to establishing the connection of the data link, the data link is switched from the full data path to the bit level data path.
Method for verifying the functionality of a digital circuit
A method, data processing system, and computer program product for verifying the functionality of a digital circuit. The method includes transmitting sequences of parallel data packets via parallel data transfer paths. Prior to receipt of at least two of the transmitted sequences, a first skew is introduced between the at least two of the transmitted sequences. This introduction includes inserting one or more parallel control data packets in the transmitted sequences, and erasing one of the control data packets, replacing one of the control data packets, and inserting another control data packet in one of the sequences. The method includes determining if an expected indicator signal is provided in the form of an overflow indicator or an underflow indicator.
Method for verifying the functionality of a digital circuit
A method, data processing system, and computer program product for verifying the functionality of a digital circuit. The method includes transmitting sequences of parallel data packets via parallel data transfer paths. Prior to receipt of at least two of the transmitted sequences, a first skew is introduced between the at least two of the transmitted sequences. This introduction includes inserting one or more parallel control data packets in the transmitted sequences, and erasing one of the control data packets, replacing one of the control data packets, and inserting another control data packet in one of the sequences. The method includes determining if an expected indicator signal is provided in the form of an overflow indicator or an underflow indicator.
Coding techniques for reference signal index modulation communications
Methods, systems, and devices for wireless communication are described that support communication of information buts based on reference signal index modulation (RS-IM). A base station and a UE may transmit a number of downlink and uplink information bits (e.g., downlink control bits, uplink control bits) using index modulation schemes applied on references signals. A base station and a UE may transmit reference signal transmissions using reference signal index modulation, in which a set of information bits may be encoded using one or more coding techniques, in conjunction with RS-IM techniques, to enhance reliability of some or all of the information bits. Error detection bits may be added to the information bits, and included when coding is performed. Coding may include channel coding, repetition of reference signals for combining at a receiving device, or any combinations thereof.
Signal delay control and related apparatuses, systems, and methods
The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.
Multi-wire electrical parameter measurements via test patterns
A measurement task is selected, where the measurement task is associated with a transmission of an encoded signal transmitted via a plurality of data lines. The encoded signal is encoded using one or more of 3-Phase, N-Phase, or N-factorial low-voltage differential signaling (LVDS) where N is at least three (3). A repeating waveform is generated corresponding to the measurement task. The repeating waveform corresponding to the measurement task is then transmitted via the plurality of data lines.
Multi-wire electrical parameter measurements via test patterns
A measurement task is selected, where the measurement task is associated with a transmission of an encoded signal transmitted via a plurality of data lines. The encoded signal is encoded using one or more of 3-Phase, N-Phase, or N-factorial low-voltage differential signaling (LVDS) where N is at least three (3). A repeating waveform is generated corresponding to the measurement task. The repeating waveform corresponding to the measurement task is then transmitted via the plurality of data lines.
Method, apparatus and system for deskewing parallel interface links
In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.
RECEPTION DEVICE, RECEPTION METHOD, TRANSMISSION DEVICE, AND TRANSMISSION METHOD
The present technology relates to a reception device, a reception method, a transmission device, and a transmission method, which are capable of implementing a high transmission rate by effectively utilizing a frequency band in channel bonding. A reception device receives a plurality of divisional streams obtained by distributing baseband (BB) frames of a BB stream which is as a stream of BB frames to a plurality of data slices and reconstructs an original BB stream on the basis of reconfiguration information which is in included in transmission control information and used for reconstructing the original BB stream from the plurality of divisional streams transmitted through the non-neighboring frequency bands when the plurality of divisional streams are transmitted through non-neighboring frequency bands. The present technology can be applied to, for example, channel bonding such as PLP bundling.
PACKAGED CIRCUIT
A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.