A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A method of analyzing a transient response of an electronic circuit includes forming a model of a retimer and receiving an analyzing the output signal of the retimer. The model includes: a signal input circuit that receives an input signal; a clock input circuit that receives a reference clock signal; a slicer that samples a signal produced by the signal input circuit based on the reference clock signal; and an output signal circuit that forms an output signal from a sample taken by the slicer and that is based on the reference clock signal.

It is presented a signal generator for providing a first signal on a first output and a second signal on a second output wherein the first signal and the second signal are provided with phase shift relative to each other. The signal generator comprises: a control loop controller; a comparator; a phase shifter, the phase shifter being arranged to provide the first signal on the first output and the second signal on the second output; and a phase error detector, the inputs of which are connected to the outputs of the phase shifter and the output of which is connected to an input of the control loop controller. The output of the control loop controller is connected in a feedback loop to a first input of the comparator, and a second input of the comparator is arranged to be connected to an alternating current source.

Embodiments of the present invention provide improved techniques for recovering clock information from data signals. In one embodiment, a general purpose device such as a real-time oscilloscope acquires a data signal. The device takes a derivative of the data signal, then computes the square or absolute of the derivative before applying a bandpass filter. The bandpass filter is a windowing function a spectrum that is wider than the clock, and has a flat top and smooth transitions on both sides. In one embodiment, at Tukey window may be used. The device finds edge crossing times of the filtered result, and applies a phase-locked loop or lowpass filter to the edge crossing times in order to recover a stable clock signal. When the improved techniques are implemented in software, they may be used with any number of different equalizers that are required by various high-speed serial data link systems.

A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

Methods, systems, and apparatus for a low-latency network interface. One of the methods includes receiving a signal having encoded data. A bit stream is generated from the received signal. Bits of the bit stream are shifted into a shift register until a feedback signal generated by a synchronization decoder is received. After the feedback signal is received, output of the shift register is descrambled to generate descrambled data. The descrambled data is stored in a first parallel register when the synchronization decoder determines that the data in the shift register is aligned to a word boundary. If the data in the first parallel register is properly aligned, the output is stored in a second parallel register.

Methods and apparatus for the flexible provision of control data within large data structures. In one exemplary embodiment, DisplayPort is modified from its existing 8B/10B line coding to 128B/130B (or 128B/132B). In one embodiment, the 128B/130B (or 128B/132B) block includes: sixteen (16) eight (8) bit command or data symbols and a two (2) bit (or four (4) bit) synchronization header. The synchronization header may provide a fixed reference to the next command symbol (for example, the symbol immediately following the synchronization header). In one variant, each command symbol is split into a first and a second portion, where the first portion identifies a control function (control symbol), and the second portion provides a reference to the next command symbol.

A communication device includes a communication interface and a processor configured to generate, transmit, receive, and process signals. The communication device generates orthogonal frequency division multiplexing (OFDM) frame(s) that include a two-dimensional (2D) start burst marker (BM), a data payload, and a 2D stop BM, and transmits the OFDM frame(s) to another communication device. Alternatively, the communication device receives OFDM frame(s) that include a 2D start BM and a 2D stop BM, and then identifies a data payload within those OFDM frame(s) based on the 2D start burst marker and a 2D stop BM. The 2D start and stop BMs are based on predetermined sequences having particular formats based on corresponding 2D sub-carrier and OFDM/A frame based structure. A receiver communication device then detects the 2D start BM and 2D stop BM within the received OFDM frame(s) based on knowledge of these predetermined sequences and particular formats.

A communication device includes a communication interface and a processor configured to generate, transmit, receive, and process signals. The communication device generates orthogonal frequency division multiplexing (OFDM) frame(s) that include a two-dimensional (2D) start burst marker (BM), a data payload, and a 2D stop BM, and transmits the OFDM frame(s) to another communication device. Alternatively, the communication device receives OFDM frame(s) that include a 2D start BM and a 2D stop BM, and then identifies a data payload within those OFDM frame(s) based on the 2D start burst marker and a 2D stop BM. The 2D start and stop BMs are based on predetermined sequences having particular formats based on corresponding 2D sub-carrier and OFDM/A frame based structure. A receiver communication device then detects the 2D start BM and 2D stop BM within the received OFDM frame(s) based on knowledge of these predetermined sequences and particular formats.

A clock correction method suitable for a communication device comprising a clock correction circuit comprises: in response to the communication device being enabled and entering an active mode, calculating, by the clock correction circuit, a clock-period ratio between a slow clock and a fast clock; in response to the communication device operating in a power-saving mode for a power-saving period, counting at least one rising edge of the slow clock received by the clock correction circuit during the power-saving period, as a cumulative number; in response to the communication device switching to an active mode, calculating the difference between an internal time of the communication device and a reference time of another communication device as a time offset; and in the active mode, adjusting, by the clock correction circuit, the clock-period ratio by using a compensation value related to the clock-period ratio, the cumulative number and the time offset.