Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

A digital demodulator for use with a Highway Addressable Remote Transducer (HART) modem is provided. Analog input signals are digitized according to a sampling clock rate to produce a discrete time signal. Filtering and edge detection allow determinations of mark or space data in a demodulated signal in conjunction with analyzing a detected signal period, a cycle period, count histories and/or an on/off signal period.

A digital demodulator for use with a Highway Addressable Remote Transducer (HART) modem is provided. Analog input signals are digitized according to a sampling clock rate to produce a discrete time signal. Filtering and edge detection allow determinations of mark or space data in a demodulated signal in conjunction with analyzing a detected signal period, a cycle period, count histories and/or an on/off signal period.

A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.

A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.

Methods and apparatus are provided for transmitting voice data in a wireless communication system, in particular there is provided an apparatus comprising an audio processing module configured to detect a period of silence in a voice signal and to output an indication of the detected period of silence, and a communication module coupled to the audio processing module and configured to transmit upload packets according to a predefined scheduling allocation, the upload packets comprising the voice signal, wherein the communication module is further configured to, upon receipt of an indication of a detected period of silence refrain from transmitting further upload packets using the predefined scheduling allocation for a predetermined period of time.

Methods and apparatus are provided for transmitting voice data in a wireless communication system, in particular there is provided an apparatus comprising an audio processing module configured to detect a period of silence in a voice signal and to output an indication of the detected period of silence, and a communication module coupled to the audio processing module and configured to transmit upload packets according to a predefined scheduling allocation, the upload packets comprising the voice signal, wherein the communication module is further configured to, upon receipt of an indication of a detected period of silence refrain from transmitting further upload packets using the predefined scheduling allocation for a predetermined period of time.

A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a dual duplex SerDes link. A transmit circuit is coupled to the I/O pad, and includes transmit rate selection circuitry to select between data transmission at a full rate or a sub-rate. A receive circuit is coupled to the I/O pad, and includes receive rate selection circuitry to select between data receipt at the full rate or the sub-rate. Data transmitted by the transmit circuit is at a data rate different than data received by the receive circuit.

A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a dual duplex SerDes link. A transmit circuit is coupled to the I/O pad, and includes transmit rate selection circuitry to select between data transmission at a full rate or a sub-rate. A receive circuit is coupled to the I/O pad, and includes receive rate selection circuitry to select between data receipt at the full rate or the sub-rate. Data transmitted by the transmit circuit is at a data rate different than data received by the receive circuit.

Methods, devices and systems for synchronizing actions taken by digital devices in a group wherein the digital devices to use a flocking protocol to establish time or behavior synchronization between individual digital devices within the group. The flocking protocol includes the transmission of synchronization information from one device to neighboring devices within the group and the processing/use of such synchronization information by the devices to synchronize the timing and/or other characteristics of their actions.