Disclosed are an apparatus and a method for soft-decision demodulating in non-square quadrature amplitude modulation. The apparatus includes: a signal receiving unit receiving a quadrature amplitude modulation (QAM) modulated signal at an m modulation degree at a transmitting side; a soft-decision bit calculating unit determining a soft-decision bit value by calculating log likelihood ratios (LLRs) for m bits of the received QAM modulated signal; and a signal decoding unit restoring the received QAM modulated signal based on the determined soft-decision bit value, in which the soft-decision bit calculating unit defines a log likelihood ratio calculation equation by approximating soft-decision boundary points of constellation points for m bits of non-square QAM having odd bits, respectively.

An electronic device receives wireless signals encoded with data in an amplitude-shift keying format. The electronic device passes the wireless signals through a low-pass filter. The low-pass filter has a cutoff frequency between a first frequency associated with data values of a first type and a second frequency associated with data values of a second type. The low-pass filter has the effect of changing the wireless signal from the amplitude-shift keying format to an on-off keying format without losing the data. The electronic device decodes the data from the wireless signal in the on-off keying format.

An electronic device receives wireless signals encoded with data in an amplitude-shift keying format. The electronic device passes the wireless signals through a low-pass filter. The low-pass filter has a cutoff frequency between a first frequency associated with data values of a first type and a second frequency associated with data values of a second type. The low-pass filter has the effect of changing the wireless signal from the amplitude-shift keying format to an on-off keying format without losing the data. The electronic device decodes the data from the wireless signal in the on-off keying format.

Disclosed is a method for the detection of more than one signals contained in a receive signal, the method comprising: down-converting the receive signal, thereby providing a down-converted signal in a complex IQ base band; at least partially cancelling the strongest user in the down-converted signal, thereby allowing for the detection of a possible secondary user.

An electronic toll collection receiver, comprising: an enveloping module configured to envelope an amplitude modulation (AM) signal; an averaging module connected to the enveloping module, configured to obtain an average value of the enveloped AM signal; a direct current blocking module connected to the enveloping module and the averaging module, configured to eliminate the average value from the enveloped AM signal; a comparing module connected to the direct current blocking module, configured to compare the average value and each of amplitude values of the enveloped AM signal; a correcting module connected to the comparing module and the directing current blocking module, configured to correct output values from the comparing module; and a decoder module connected to the correcting module, configured to decode the corrected output values from the correcting module.

An electronic toll collection receiver, comprising: an enveloping module configured to envelope an amplitude modulation (AM) signal; an averaging module connected to the enveloping module, configured to obtain an average value of the enveloped AM signal; a direct current blocking module connected to the enveloping module and the averaging module, configured to eliminate the average value from the enveloped AM signal; a comparing module connected to the direct current blocking module, configured to compare the average value and each of amplitude values of the enveloped AM signal; a correcting module connected to the comparing module and the directing current blocking module, configured to correct output values from the comparing module; and a decoder module connected to the correcting module, configured to decode the corrected output values from the correcting module.

In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.