An information handling system includes a high-speed data communication link and a processor. The link includes lanes that each includes a transmitter with an equalization setting and a receiver. The processor initiates a training of the high-speed data communication interface to determine a setting value for the equalization setting for each lane, determines a lane quality value for each lane based upon the associated setting value, determines a link score based on the lane quality values, and determines that the lane quality score is outside a threshold range. In response to determining that the lane quality score is outside the threshold range, the processor selects a lane that has a lane quality value that has a greater magnitude than the lane quality values of all other lanes, increases the equalization setting of the first lane, and initiates a retraining of the other lanes.

An information handling system includes a high-speed data communication link and a processor. The link includes lanes that each includes a transmitter with an equalization setting and a receiver. The processor initiates a training of the high-speed data communication interface to determine a setting value for the equalization setting for each lane, determines a lane quality value for each lane based upon the associated setting value, determines a link score based on the lane quality values, and determines that the lane quality score is outside a threshold range. In response to determining that the lane quality score is outside the threshold range, the processor selects a lane that has a lane quality value that has a greater magnitude than the lane quality values of all other lanes, increases the equalization setting of the first lane, and initiates a retraining of the other lanes.

In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

Vector modulation is illustrated. A method includes receiving an input signal. The input signal is split into a first 0° output and a 90° output. The first 0° output is split into a second 0° output and a first 180° output using a continuous transmission line. The 90° output is split into a third 0° output and a second 180° output using a continuous transmission line. The second 0° output, the first 180° output, the third 0° output, and the second 180° output are modulated. The modulated second 0° output, the first 180° output, the third 0° output, and the second 180° output are recombined to produce an output signal, where all four of the modulated second 0° output, the first 180° output, the third 0° output, and the second 180° output are used to create the output signal.

A device that comprises a plurality of distributed transceivers, a central processor and a network management engine may be configured to function as relay device, relaying an input data stream from a source device to at least one other device. The relaying may include configuring one or more of the plurality of distributed transceivers to particular mode of relay operation and receiving the input data stream from the source device via at least one of the configured one or more of the plurality of distributed transceivers. The relaying may also include transmitting at least one relay data stream corresponding to the input data stream to the at least one other device, via at least one of the configured one or more of the plurality of distributed transceivers.

A device that comprises a plurality of distributed transceivers, a central processor and a network management engine may be configured to function as relay device, relaying an input data stream from a source device to at least one other device. The relaying may include configuring one or more of the plurality of distributed transceivers to particular mode of relay operation and receiving the input data stream from the source device via at least one of the configured one or more of the plurality of distributed transceivers. The relaying may also include transmitting at least one relay data stream corresponding to the input data stream to the at least one other device, via at least one of the configured one or more of the plurality of distributed transceivers.

Electronic device and method for driving electronic device. The electronic device includes battery, power management integrated circuit (PMIC) configured to control charging status of battery, coil, wireless power circuit electrically connected to coil, communication circuit electrically connected to coil, and processor, wherein processor is configured to, when the wireless power circuit is in a transmission (Tx) mode, transmit a wireless power signal through the coil by using the wireless power circuit, and transmit a signal obtained by frequency shift keying (FSK)-modulating a transmission device parameter by using the communication circuit, to an external electronic device through the coil, and when the wireless power circuit is in a reception (Rx) mode, receive wireless power by using the wireless power circuit to charge the battery, and transmit a signal obtained by amplitude shift keying (ASK)-modulating a reception device parameter by using the communication circuit, to the external electronic device through the coil.

Electronic device and method for driving electronic device. The electronic device includes battery, power management integrated circuit (PMIC) configured to control charging status of battery, coil, wireless power circuit electrically connected to coil, communication circuit electrically connected to coil, and processor, wherein processor is configured to, when the wireless power circuit is in a transmission (Tx) mode, transmit a wireless power signal through the coil by using the wireless power circuit, and transmit a signal obtained by frequency shift keying (FSK)-modulating a transmission device parameter by using the communication circuit, to an external electronic device through the coil, and when the wireless power circuit is in a reception (Rx) mode, receive wireless power by using the wireless power circuit to charge the battery, and transmit a signal obtained by amplitude shift keying (ASK)-modulating a reception device parameter by using the communication circuit, to the external electronic device through the coil.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.