An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

A mixer in a receiver converts a sounding sequence of alternating ones and zeros to an intermediate frequency signal. A digital mixer converts the intermediate frequency signal to a baseband signal that contains a positive tone and a negative tone. A frequency offset correction circuit generates frequency offset corrections based on frequency offset estimates of the frequency offset between a transmitter of the sounding sequence and the receiver. A frequency adjustment circuit adjusts a frequency of the mixer or the digital mixer to thereby center the positive tone and the negative tone around DC. DFT circuits perform single bin DFTs respectively centered on the positive and negative tones. Phases of the positive and negative tones are calculated based on outputs of the DFT circuits and the phases are used to determine fractional time value associated with a distance measurement between the transmitter and receiver.

A method for decoding an RF signal bearing a sequence of transmitted symbols modulated by CPM. The method includes, at the receiver: estimating model parameters {h, ω, Φ.sub.0} among which h characterizes a modulation index, ω characterizes a carrier frequency offset and Φ.sub.0 characterizes an initial phase offset, and detecting received symbols corresponding to said transmitted symbols of the sequence, wherein, at time nT where T is a symbol duration, the parameters {h, ω, Φ.sub.0} are estimated by solving a system of three linear equations whose: three unknowns {ĥ.sup.(n), {circumflex over (ω)}.sup.(n), {circumflex over (Φ)}.sub.0.sup.(n)} are respectively function of said model parameters {h, ω, Φ.sub.0}, and coefficients {B.sup.(n), C.sup.(n), D.sup.(n), F.sup.(n), G.sup.(n), H.sup.(n), v.sub.1.sup.(n), v.sub.2.sup.(n), v.sub.3.sup.(n)} are computed in a recursive way in function of: a sequence of symbols {â.sub.n} corresponding to the sequence of transmitted symbols up to time nT, and measured phases {Ψ.sub.k} of samples {y.sub.k} of the RF signal received from time (n−1)T to time nT.

An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

A diversity receiver synchronizes and mixes multiple input signals. In one embodiment, the receiver demodulates the multiple input signals prior to synchronizing, converts the demodulated multiple input signals from analog signals to digital signals, synchronizes the demodulated digital signals, converts the synchronized demodulated digital signals to analog signals and mixes the synchronized demodulated analog signals based on a characteristic of the input signals existing prior to the demodulating.

A method and a circuit are arranged for adapting a first reference value for generating a first bit stream from an input signal by a first amplitude adapting unit. The input signal comprises a first and a second signal. The first signal and the second signal form a baseband sum signal. A first non-linear component demodulates the input signal and outputs a demodulated input signal. The amplitude adapting unit outputs the first bit stream from the demodulated input signal on the basis of a first reference value. A reference-value adapting unit comprises a detection unit which detects the first and the second signal. Upon discontinuation of the first and second signals, an adjusting unit adjusts the first reference value to a basic reference value.

A method and a circuit are arranged for adapting a first reference value for generating a first bit stream from an input signal by a first amplitude adapting unit. The input signal comprises a first and a second signal. The first signal and the second signal form a baseband sum signal. A first non-linear component demodulates the input signal and outputs a demodulated input signal. The amplitude adapting unit outputs the first bit stream from the demodulated input signal on the basis of a first reference value. A reference-value adapting unit comprises a detection unit which detects the first and the second signal. Upon discontinuation of the first and second signals, an adjusting unit adjusts the first reference value to a basic reference value.

A quadrature detection unit subjects an FM signal to quadrature detection using a local oscillation signal and outputs a base band signal. A first correction unit and a second correction unit correct the base band signal using a DC offset correction value. A DC offset detection unit subjects the corrected base band signal to rectangular to polar conversion and derives the DC offset correction value such that amplitudes in a plurality of phase domains defined in an IQ plane approximate each other. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. An addition unit adds an offset to the detection signal. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal based on the detection signal to which the offset is added.