There is disclosed a method for operating a wireless device in a wireless communication network, the method comprising modulating a plurality of input bits (N), wherein modulating comprises choosing a first number (k) of frequencies from a predetermined set of a total number (NF) of frequencies, the first number (k) being larger than 1, and performing quadrature amplitude modulation to a second number (NQ) on each of the first number (k) of frequencies. There are further disclosed related methods and devices.

A phase detection system includes first and second phase mixing circuits in signal communication with a signal phase adjuster module. The first mixing circuit generates a first digital modulated frequency signal based on an input signal and a first reference phase signal. The second mixing circuit generates a second digital modulated frequency signal based on the input signal and a second reference phase signal, which phase shifted with respect to the first reference phase signal. The phase detection system further includes a phase identification (ID) module in signal communication with the first mixing circuit and the second mixing circuit. The phase ID module generates a phase signal based on the first digital modulated frequency signal and the second digital modulated frequency signal. The phase signal indicates a phase of the input signal.

A phase detection system includes first and second phase mixing circuits in signal communication with a signal phase adjuster module. The first mixing circuit generates a first digital modulated frequency signal based on an input signal and a first reference phase signal. The second mixing circuit generates a second digital modulated frequency signal based on the input signal and a second reference phase signal, which phase shifted with respect to the first reference phase signal. The phase detection system further includes a phase identification (ID) module in signal communication with the first mixing circuit and the second mixing circuit. The phase ID module generates a phase signal based on the first digital modulated frequency signal and the second digital modulated frequency signal. The phase signal indicates a phase of the input signal.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (RF) signal. An example receiver includes a plurality of high-pass filters. The receiver includes a demodulator configured to demodulate an RF signal received at an input of the demodulator and configured to output a demodulated signal. The receiver also includes a plurality of high-pass filters connected to an output of the demodulator. The plurality of high-pass filters are configured to receive the demodulated signal and configured to high-pass filter the demodulated signal. The plurality of high-pass filters are configured to operate with a first set of filter responses during a first time period of the demodulated signal and configured to operate with a second set of filter responses during a second time period of the demodulated signal.

Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (RF) signal. An example receiver includes a plurality of high-pass filters. The receiver includes a demodulator configured to demodulate an RF signal received at an input of the demodulator and configured to output a demodulated signal. The receiver also includes a plurality of high-pass filters connected to an output of the demodulator. The plurality of high-pass filters are configured to receive the demodulated signal and configured to high-pass filter the demodulated signal. The plurality of high-pass filters are configured to operate with a first set of filter responses during a first time period of the demodulated signal and configured to operate with a second set of filter responses during a second time period of the demodulated signal.

A method and terminal device for reducing an image distortion are provided. The terminal device generates a radio frequency signal from a first path that includes first and second low pass filters of in-phase and quadrature phase paths, produces a decomposed signal having in-phase and quadrature phase components in digital form based on the radio frequency signal, and determines a phase mismatch between the in-phase and quadrature phase components. Then the terminal device generates a bandwidth adjustment value based on the determined phase mismatch, further generates, based on the bandwidth adjustment value, first and second bandwidth control signals; and adjusts a bandwidth of first and second low pass filters based on the first and second bandwidth control signals to reduce the phase mismatch.

Systems and techniques for communicating data as a function of frequency are presented. In an implementation, a system includes a microelectromechanical systems (MEMS) sensor, a digital signal processor and a frequency detection circuit. The digital signal processor is coupled to the MEMS sensor. The frequency detection circuit receives data encoded as a function of frequency from the digital signal processor via a clock communication channel.

Systems and techniques for communicating data as a function of frequency are presented. In an implementation, a system includes a microelectromechanical systems (MEMS) sensor, a digital signal processor and a frequency detection circuit. The digital signal processor is coupled to the MEMS sensor. The frequency detection circuit receives data encoded as a function of frequency from the digital signal processor via a clock communication channel.