A phase detection system includes first and second phase mixing circuits in signal communication with a signal phase adjuster module. The first mixing circuit generates a first digital modulated frequency signal based on an input signal and a first reference phase signal. The second mixing circuit generates a second digital modulated frequency signal based on the input signal and a second reference phase signal, which phase shifted with respect to the first reference phase signal. The phase detection system further includes a phase identification (ID) module in signal communication with the first mixing circuit and the second mixing circuit. The phase ID module generates a phase signal based on the first digital modulated frequency signal and the second digital modulated frequency signal. The phase signal indicates a phase of the input signal.

A method of performing carrier frequency offset (CFO) estimation and/or time offset (TO) estimation at a radio equipment in a mobile communications system. The method allows, for each of a plurality of synchronization signal (SS) blocks (SSBs) in a SS Burst detected at said radio equipment, determining a CFO estimation and/or a TO estimation based on network information signal prediction. The method includes selecting at least some of said detected SSBs in said SSB Burst and combining the CFO estimations and/or the TO estimations to obtain improved CFO compensation and/or TO compensation for signal processing at said radio equipment.

Disclosed are techniques to compensate frequency systematic known error (FSKE) in reflector or initiator radios using a hybrid RF-digital approach in multi-carrier phase-based ranging. The hybrid RF-digital approach combines a coarse frequency compensation technique in the RF domain and a fine frequency compensation technique in the digital domain to remove the FSKE across all carrier frequencies from a device. The coarse frequency compensation performed in the RF domain may use a PLL to multiply the crystal frequency to arrive close to a target carrier frequency to compensate for a coarse portion of the known FSKE at the target frequency. The fine frequency compensation may use digital techniques to remove the remaining portion of the known FSKE not compensated by the RF. The hybrid approach reduces the number of fractional bits in the multiplier of the PLL when compared to an approach that uses only the RF-PLL to remove the FSKE.

A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

Techniques for blind distributed multi-user MIMO enable simultaneous decoding of multiple concurrent wireless transmissions without the need for coordination between wireless devices or a measurement phase. Wireless devices are permitted to transmit independently and at arbitrary times. Concurrent transmissions from wireless devices superimpose in the wireless channel and are received at various base stations. The base stations forward received data samples to a central entity (e.g., a cloud computing service), which uses known preambles to reliably estimate CFOs and channels between the transmitting devices and the receiving base stations while simultaneously recovering the data samples of the individual data streams.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.