A computing device operating according to a frequency division multiplexed protocol in which communication occurs over a signal formed from a plurality of sub-channels selected from anywhere in a frequency spectrum. A computing device may select sub-channels cognitively by using information about sub-channels previously deemed suitable or unsuitable by that computing device or other computing devices. A described technique for determining sub-channel suitability includes analyzing radio frequency energy in the sub-channel to detect signals generated by another computing device or high noise levels. Information may also be used to cognitively select sub-channels to be analyzed, such as by first selecting for analysis previously-used sub-channels.

A computing device operating according to a frequency division multiplexed protocol in which communication occurs over a signal formed from a plurality of sub-channels selected from anywhere in a frequency spectrum. A computing device may select sub-channels cognitively by using information about sub-channels previously deemed suitable or unsuitable by that computing device or other computing devices. A described technique for determining sub-channel suitability includes analyzing radio frequency energy in the sub-channel to detect signals generated by another computing device or high noise levels. Information may also be used to cognitively select sub-channels to be analyzed, such as by first selecting for analysis previously-used sub-channels.

A method and apparatus are provided. The method includes receiving a signal from a transceiver, demapping a bit pattern encoded within the signal, detecting a preamble based on the demapped bit pattern, and synchronizing the transceiver to a receiver using the preamble, wherein demapping the bit pattern is based on weighting coefficients.

The present invention relates to a method of simultaneously performing packet detection, symbol timing acquisition, and carrier frequency offset estimation in parallel using multiple correlation detection and a Bluetooth apparatus using the same, in which the Bluetooth apparatus receiving a frequency modulated signal includes a frequency demodulating unit converting the received signal into a similar amplitude modulated signal; and multiple correlation detectors generating multiple correlation indices from the converted signal, on a basis of an access address received from a link layer and a plurality of carrier frequency offset search windows. According to the present invention, since packet detection, symbol timing acquisition and carrier frequency offset estimation are simultaneously performed in parallel in the relatively long access address reception interval instead of the short preamble signal reception interval.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises:

a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet;

a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information;

an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion sends a timeout warning signal to the address checking circuit portion using a handshaking channel therebetween; said address checking circuit portion being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.

A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises:

a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet;

a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information;

an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion sends a timeout warning signal to the address checking circuit portion using a handshaking channel therebetween; said address checking circuit portion being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.