An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.

A method of operating a hypercube network of processing devices includes determining that a plurality of the processing devices are storing data to be processed at a single processing device, obtaining the addresses of the plurality of processing devices storing the data to be processed, determining the most common number for each digit of the addresses of the plurality of processing devices storing the data to be processed, generating a new address comprising the determined most common number for each digit, and transferring the data to be processed to the processing device with the generated new address.

An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.

Embodiments for a method for enhancing communication for operating along with a plurality of cooperating communication enhancement modules are disclosed. The communication enhancement module receives a STANAG 4586 message from an upstream module and determine whether a point-to-point wireless connection is available to the destination. If a point-to-point wireless connection is available, the module sends a message over the point-to-point wireless connection to the destination. If a point-to-point wireless connection is not available, the module identifies a multi-hop path to the destination via at least one other communication enhancement module, modifies the STANAG 4586 message to create a modified message having a format corresponding to the communication enhancement modules, and send the modified message to a next hop communication enhancement module on the multi-hop path for directing toward the destination.

A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.

In accordance with one or more preferred implementations, an overlay network in the form of a dispersive virtual network is implemented utilizing data deflects to implement and facilitate routing in a data plane and call processing deflects to implement and facilitate routing in a control plane. Various nodes in the dispersive virtual network, such as end devices running dispersive virtual networking client software, establish communication channels to these deflects running dispersive virtual networking protocols transported by user datagram protocol (UDP) frames, transmission control protocol (TCP) streams, and hypertext transfer protocol (HTTP) streams. In accordance with one or more preferred implementations, software allows nodes in a dispersive virtual network to automatically detect the channel types that are available at the time the node must initiate a new session, and automatically configure the most efficient communication channel without requiring input from an end user or from a network administrator.

The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.