Patent classifications
H04L45/06
Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
UAV communication enhancement module
Embodiments for a method for enhancing communication for one or more unmanned aerial vehicles (UAVs) are also disclosed. The method includes receiving, at a first communication enhancement module of a first UAV, a STANAG 4586 message from an upstream module. The STANAG 4586 message indicates a MUCS as its destination. A multi-hop path to the MUCS via at least one other communication enhancement module is identified. It is determined whether a point-to-point wireless link or the multi-hop route is a better path to the MUCS. If a point-to-point wireless link is a better path, the message is sent over the point-to-point wireless link to the MUCS. If the multi-hop route is a better path, the message is modified to create a modified message having a format corresponding to the communication enhancement modules. The modified message is then sent to the other communication enhancement module(s) on the multi-hop path.
STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY
Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.
Method for routing a message at a wireless node in a wireless network
Aspects of the disclosure provide a wireless node in a wireless network with a grid topology for routing a message. The wireless node includes circuitry configured to receive a message including a destination node identification number, calculate a destination column and a destination row based on the destination node identification number, determine a next hop address based on the destination column and the destination row, and transmit the message including the next hop address to a next hop node.
Wireless node/wireless network system
Aspects of the disclosure provide a wireless node in a wireless network with a grid topology for routing a message. The wireless node includes circuitry configured to receive a message including a destination node identification number, calculate a destination column and a destination row based on the destination node identification number, determine a next hop address based on the destination column and the destination row, and transmit the message including the next hop address to a next hop node.
Reverse metric advertisement for border gateway protocol route reflection inhierarchical networks
In one example, a method includes by a first network device positioned on a border of a first area of a multi-area hierarchical network and a second area of the multi-area hierarchical network, determining a cost associated with sending network traffic from a client group to the first network device, wherein the client group is positioned in the first area, the first area and the second area being distinct routing domains of the multi-area hierarchical network; and outputting, by the first network device to a second network device positioned in the second area, a routing advertisement that specifies the determined cost as a reverse metric. In some examples, a route reflector receives the routing advertisement and based on the cost from the client group to the area border network device, selects an egress point from among a plurality of egress points of the multi-area hierarchical network.
NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS
Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to clear, such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.
DATA TRANSPORT USING GEOGRAPHICAL LOCATION
A public network links a plurality of nodes, each associated with at least one network address. A transport network connects a plurality of routers, each of which is also connected to the public network. A database holds geographical location information associated with respective network addresses on the public network. The database is used to determine which of the routers is closest to geographical locations associated with the network addresses. Information is stored that identifies these closest routers. The information is suitable for use in a routing protocol for routing data packets through the transport network to a destination outside the transport network.
Parallel processing apparatus and non-transitory computer-readable storage medium
A parallel processing apparatus including a plurality of compute nodes and a management node including a first processor configured to execute a process including collecting failure information regarding a plurality of ports of the plurality of compute nodes, and transmitting, to the plurality of compute nodes, failed port information including information on a failed port of the plurality of ports when an update in the failure information is detected in the collecting, wherein each of the plurality of compute nodes includes a second processor configured to execute a process including determining a retransmission route based on the failed port information when an inter-compute node communication in a low-level communication library has failed, and re-executing the inter-node communication by using the determined retransmission route.
Deadlock-free routing in lossless multidimensional cartesian topologies with minimal number of virtual buffers
An apparatus includes a network interface and a processor. The network interface is configured to communicate with a network that includes a plurality of switches interconnected in a Cartesian topology having multiple dimensions. The processor is configured to predefine an order among the dimensions of the Cartesian topology, to search for a preferred route via the network from a source switch to a destination switch, by evaluating candidate routes based at least on respective numbers of switches along the candidate routes for which traversal to a next-hop switch changes from one of the dimensions to another of the dimensions opposite to the predefined order, and to configure one or more of the switches in the network to route packets from the source switch to the destination switch along the preferred route.