H04L47/30

TRAFFIC SHAPING METHOD AND APPARATUS
20230239248 · 2023-07-27 ·

This application provides a traffic shaping method and apparatus. The method includes: A packet marking apparatus receives a first packet; the packet marking apparatus determines an enqueuing queue of the first packet; and the packet marking apparatus marks a queue identifier of the first packet as a queue identifier of the enqueuing queue of the first packet, and then sends the queue identifier of the first packet to a packet output apparatus, where the packet output apparatus is configured to send, based on the queue identifier of the first packet, the first packet to a corresponding queue for outputting. Therefore, packet output time after traffic shaping can be determined.

TRAFFIC SHAPING METHOD AND APPARATUS
20230239248 · 2023-07-27 ·

This application provides a traffic shaping method and apparatus. The method includes: A packet marking apparatus receives a first packet; the packet marking apparatus determines an enqueuing queue of the first packet; and the packet marking apparatus marks a queue identifier of the first packet as a queue identifier of the enqueuing queue of the first packet, and then sends the queue identifier of the first packet to a packet output apparatus, where the packet output apparatus is configured to send, based on the queue identifier of the first packet, the first packet to a corresponding queue for outputting. Therefore, packet output time after traffic shaping can be determined.

Generating, at least in part, and/or receiving, at least in part, at least one request

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Generating, at least in part, and/or receiving, at least in part, at least one request

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Flow-based management of shared buffer resources
20230022037 · 2023-01-26 ·

An apparatus for controlling a Shared Buffer (SB), the apparatus including an interface and a SB controller. The interface is to access flow-based data counts and admission states. The SB controller is to perform flow-based accounting of packets received by a network device coupled to a communication network, for producing flow-based data counts, each flow-based data count associated with one or more respective flows, and to generate admission states based at least on the flow-based data counts, each admission state being generated from one or more respective flow-based data counts.

Queue protection using a shared global memory reserve

The subject technology relates to the management of a shared buffer memory in a network switch. Systems, methods, and machine readable media are provided for receiving a data packet at a first network queue from among a plurality of network queues, determining if a fill level of a queue in a shared buffer of the network switch exceeds a dynamic queue threshold, and in an event that the fill level of the shared buffer exceeds the dynamic queue threshold, determining if a fill level of the first network queue is less than a static queue minimum threshold.

Queue protection using a shared global memory reserve

The subject technology relates to the management of a shared buffer memory in a network switch. Systems, methods, and machine readable media are provided for receiving a data packet at a first network queue from among a plurality of network queues, determining if a fill level of a queue in a shared buffer of the network switch exceeds a dynamic queue threshold, and in an event that the fill level of the shared buffer exceeds the dynamic queue threshold, determining if a fill level of the first network queue is less than a static queue minimum threshold.

PROCESSING OF ETHERNET PACKETS AT A PROGRAMMABLE INTEGRATED CIRCUIT

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

PROCESSING OF ETHERNET PACKETS AT A PROGRAMMABLE INTEGRATED CIRCUIT

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Congestion avoidance in a network switch device
11558298 · 2023-01-17 · ·

Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting congestion in the internal memory of the network switch device, a flow control engine triggers, during respective timeslots of a timing schedule and while the flow control engine continues to monitor congestion in the internal memory of the network switch device, transmission of respective flow control messages via different subsets of ports, among the plurality of ports, to control flow of packets from different subsets of upstream network device, among the plurality of upstream network devices, to the network switch device so that flow control is distributed over time among upstream network devices of the plurality of upstream network devices.