H04L49/101

Connectors for a networking device with orthogonal switch bars

Connectors for a networking device may be provided. A networking device may comprise a first plurality of switch bars each comprising a first switch type arranged parallel to one another, a second plurality of switch bars each comprising a second switch type arranged parallel to one another, and a third plurality of switch bars each comprising a third switch type arranged parallel to one another. The first plurality of switch bars, the second plurality of switch bars, and the third plurality of switch bars may be arranged orthogonally. A first one of the first plurality of switch bars may be connected to a first one of the second plurality of switch bars via a retractable mechanical connector mechanism.

PACKET SWITCHES

Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

PACKET SWITCHES

Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

FRAME DATA PROCESSING

A circuit for use in frame filtering is disclosed. The circuit includes a plurality of comparator units. Each comparator unit configured, in response to receiving at least a part of a data frame, to perform a determination whether data in a portion of the at least part of the data frame matches respective reference data and to provide a result to a comparator unit output based on the determination. The circuit includes a crossbar switch having crossbar inputs coupled to respective comparator unit outputs and configured to provide sets of crossbar switch outputs via configurable interconnects; and a set of result-combining logic units, each result-combining logic unit coupled to a respective set of crossbar switch outputs, and configured to provide a respective logic unit output.

FRAME DATA PROCESSING

A circuit for use in frame filtering is disclosed. The circuit includes a plurality of comparator units. Each comparator unit configured, in response to receiving at least a part of a data frame, to perform a determination whether data in a portion of the at least part of the data frame matches respective reference data and to provide a result to a comparator unit output based on the determination. The circuit includes a crossbar switch having crossbar inputs coupled to respective comparator unit outputs and configured to provide sets of crossbar switch outputs via configurable interconnects; and a set of result-combining logic units, each result-combining logic unit coupled to a respective set of crossbar switch outputs, and configured to provide a respective logic unit output.

CROSSBAR MULTIPATHING FOR MULTICAST PERFORMANCE IN TILED SWITCHES

A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

CROSSBAR MULTIPATHING FOR MULTICAST PERFORMANCE IN TILED SWITCHES

A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

Universal radio frequency router with an automatic gain control

Various embodiments are described herein for a radio frequency (RF) signal router. In one example embodiment, the RF router comprises a controller, an input stage, an intermediate stage and an output stage. The input stage includes RF input terminals, pre-processing circuit and input processors, where each RF input terminal receives an incoming RF signal, each pre-processing circuit processes the incoming RF signal based on its power level, and each input processor adjusts a power level of an input RF signal based on a first controller signal to generate a processed input RF signal. The intermediate stage comprises intermediate switch matrices coupled to a controller and input processors, and configured to route intermediate RF signals. The output stage comprises output processors coupled to the controller, where each output processor is configured to adjust a power level of an output RF signal based on a second controller signal and generate a processed output RF signal, and where the second controller signal corresponds to the first controller signal.

Universal radio frequency router with an automatic gain control

Various embodiments are described herein for a radio frequency (RF) signal router. In one example embodiment, the RF router comprises a controller, an input stage, an intermediate stage and an output stage. The input stage includes RF input terminals, pre-processing circuit and input processors, where each RF input terminal receives an incoming RF signal, each pre-processing circuit processes the incoming RF signal based on its power level, and each input processor adjusts a power level of an input RF signal based on a first controller signal to generate a processed input RF signal. The intermediate stage comprises intermediate switch matrices coupled to a controller and input processors, and configured to route intermediate RF signals. The output stage comprises output processors coupled to the controller, where each output processor is configured to adjust a power level of an output RF signal based on a second controller signal and generate a processed output RF signal, and where the second controller signal corresponds to the first controller signal.

Inter-packet communication of machine learning information

A network switch includes one or more queues to hold packets received from a first input flow and a second input flow. The network switch also includes a packet communication switch configured to access a first header of a first packet in the one or more queues and a second header of a second packet in the one or more queues. The first header includes first machine learning (ML) information that represents a first set of state transition probabilities under a set of actions performed at the network switch. The second header includes second ML information that represents a second set of state transition probabilities under the set of actions performed at the network switch. The packet communication switch is configured to selectively modify the first header or the second header based on a comparison of the first ML information and the second ML information.