In an example, a node in a network includes four ports coupled to respective nodes via respective links. A first port and a third port are coupled to respective nodes via respective near links and a second port and a fourth port are coupled to respective nodes via respective skip links. The node further includes at least one processor configured to send a first message in a first direction via the second port, and the first message includes a first destination address that corresponds to the second side of the node. The at least one processor is further configured to send a second message in a second direction via the fourth port, and the second message includes a second destination address that corresponds to the first side of the node.

A method for traffic management of proprietary data, in a network system comprising a gateway and a sensor communicatively coupled to the gateway via a data bus, includes determining, by a processor of a bridging device, whether a dedicated pipeline for transmission to the gateway is available, in response to determining that the dedicated pipeline is available, transmitting, by the processor, a request for the dedicated pipeline, determining, by the processor, whether the dedicated pipeline has been established between the bridging device and the gateway, and in response to determining that the dedicated pipe has been established, requesting, by the processor, the proprietary data from the sensor, transmitting, by the processor, the proprietary data from the sensor to the gateway via the dedicated pipeline, and transmitting, by the processor, a dedicated pipeline release signal to the gateway indicating release of dedicated pipeline between the bridging device and the gateway.

A physical-layer cross connect (PLCC) includes a system-bus interface; a switching circuit having multiple externally accessible data ports, an internal-only PLCC-controller port, and a data bus that is dynamically configurable among the externally accessible data ports and the internal-only PLCC-controller port; transceivers connected to the externally accessible data ports and to a signal bus; data jacks connected to the transceivers; and a PLCC controller interfaced with the system-bus interface, the data bus, the signal bus, and the internal-only PLCC-controller port and configured to: receive path-configuration commands from a communication-path-management controller and responsively configure connections on the data bus; receive mirrored copies of inbound data by selectively configuring connections on the data bus between the internal-only PLCC-controller port and the various externally accessible data ports; analyze the mirrored copies of inbound data to determine at least one informational characteristic; and report the determined informational characteristic(s) to the communication-path-management controller.

A communication system with train bus architecture is described. The communication system with the train bus architecture comprises a coupling device for transmitting a first instruction packet string having instruction packets via first path; the controlled module for receiving the first instruction packet string via first path, wherein the controlled module selects one instruction packet from the instruction packets, replaces the selected instruction packet by first response packet for forming second instruction packet string, and processes the selected instruction packet to generate a second response packet; and a terminal device for receiving the second instruction packet string via the first path, and for transmitting the second instruction packet string back to the coupling device via the at least one controlled module along a second path from the terminal device to the coupling device wherein the first path is connected to the second path to form train bus architecture.

A bufferless ring network including at least two nodes and at least two timeslots, the at least two timeslots include a dedicated timeslot, and a first node in the bufferless ring network has use permission for the dedicated timeslot. The first node is configured to, in a state of having the use permission for the dedicated timeslot, detect whether all dedicated timeslots that pass through the first node are available, set a permission switch signal, and cancel the use permission for the dedicated timeslot according to the permission switch signal after detecting that all the dedicated timeslots that pass through the first node are available. A remaining node in the bufferless ring network is configured to obtain the use permission for the dedicated timeslot according to the permission switch signal. The remaining node is a node that needs to use the dedicated timeslot.

Significantly optimized multi-stage networks including scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal wires and vertical wires to route large scale partial multi-stage hierarchical networks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are disclosed. The optimized multi-stage networks in each block employ one or more slices of rings of stages of switches with inlet and outlet links of partial multi-stage hierarchical networks connecting to rings from either left-hand side or right-hand side; and employ hop wires or multi-drop hop wires wherein hop wires or multi-drop wires are connected from switches of stages of rings of slices of a first partial multi-stage hierarchical network to switches of stages of rings of slices of the first or a second partial multi-stage hierarchical network.

Significantly optimized multi-stage networks including scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal wires and vertical wires to route large scale partial multi-stage hierarchical networks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are disclosed. The optimized multi-stage networks in each block employ one or more slices of rings of stages of switches with inlet and outlet links of partial multi-stage hierarchical networks connecting to rings from either left-hand side or right-hand side; and employ hop wires or multi-drop hop wires wherein hop wires or multi-drop wires are connected from switches of stages of rings of slices of a first partial multi-stage hierarchical network to switches of stages of rings of slices of the first or a second partial multi-stage hierarchical network.

Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.

Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.

A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.