Some embodiments provide a network forwarding IC with packet processing pipelines, at least one of which includes a parser, a set of match-action stages, and a deparser. The parser is configured to receive a packet and generate a PHV including a first number of data containers storing data for the packet. A first match-action stage is configured to receive the PHV from the parser and expand the PHV to a second, larger number of data containers storing data for the packet. Each of a set of intermediate match-action stage is configured to receive the expanded PHV from a previous stage and provide the expanded PHV to a subsequent stage. A final match-action stage is configured to receive the expanded PHV and reduce the PHV to the first number of data containers. The deparser is configured to receive the reduced PHV from the final match-action stage and reconstruct the packet.

System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

The disclosed method is applicable to a many-core system. The method includes: acquiring multiple pieces of .routing information, each of which includes two logical nodes and a data transmission amount between the two logical nodes; determining a piece of unprocessed routing information with a maximum data transmission amount as current routing information; mapping each unlocked logical node of the current routing information to one unlocked processing node, and locking the mapped logical node and processing node, wherein if there is an unlocked edge processing node, the unlocked logical node is mapped to the unlocked edge processing node; and returning, if there is at least one unlocked logical node, to the step of determining the piece of unprocessed routing information with the maximum data transmission amount as the current routing information.

Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers without reducing the range of packet lengths supported. A packet header includes a fixed-width length field. Using a linear encoding, the maximum packet size is a linear function of the fixed-width length field. Thus, to expand the range of sizes available, either the granularity of the field must be decreased (e.g., by changing the measure of the field from flits to double-flits) or the size of the field must be increased (e.g., by changing the size of the field from 4 bits to 5 bits). However, by using a non-linear encoding, the difference between the minimum and maximum size can be increased without decreasing the granularity within a first range of field values and without increasing the size of the length field.

Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers without reducing the range of packet lengths supported. A packet header includes a fixed-width length field. Using a linear encoding, the maximum packet size is a linear function of the fixed-width length field. Thus, to expand the range of sizes available, either the granularity of the field must be decreased (e.g., by changing the measure of the field from flits to double-flits) or the size of the field must be increased (e.g., by changing the size of the field from 4 bits to 5 bits). However, by using a non-linear encoding, the difference between the minimum and maximum size can be increased without decreasing the granularity within a first range of field values and without increasing the size of the length field.

The present subject matter relates to one or more devices, systems and/or methods for providing wireless telecommunication services. A Small Form Factor Pluggable Unit (SFP) incorporates wireless capabilities, and includes an integrated or an external antenna. The SFP comprises wireless circuitry for transmitting and receive multiple and distinct wireless signals, including Wi-Fi and Bluetooth for communicating with various equipment, devices and/or networks.

The present subject matter relates to one or more devices, systems and/or methods for providing wireless telecommunication services. A Small Form Factor Pluggable Unit (SFP) incorporates wireless capabilities, and includes an integrated or an external antenna. The SFP comprises wireless circuitry for transmitting and receive multiple and distinct wireless signals, including Wi-Fi and Bluetooth for communicating with various equipment, devices and/or networks.

Provided in the present disclosure are a data processing method and apparatus, and an electronic device, the method includes: determining a plurality of candidate data pieces, where the candidate data pieces are provided from corresponding data sources; and determining a target data piece based on priorities of the data sources corresponding to the plurality of candidate data pieces in a current cycle, wherein a same data source has different priorities in different processing cycles, and priority sequence numbers of a same data source in different processing cycles satisfy a nonlinear relationship.