A gateway device receives interface information sent by an interface extension device, where an Ethernet interface of the interface extension device is connected to a target Ethernet interface of the gateway device, and the interface information includes an interface type and a media access control (MAC) address of a first non-Ethernet interface of the interface extension device. The gateway device creates a first virtual interface on the target Ethernet interface based on the interface information, where the first virtual interface corresponds to the first non-Ethernet interface, and an interface type of the first virtual interface is an Ethernet interface. The gateway device sends an interface creation success notification to the interface extension device. The gateway device may obtain data of the first non-Ethernet interface through the first virtual interface, thereby implementing interface extension of the gateway device.

System and method for supporting scalable bitmap based P_Key table in a high performance computing environment. A method can provide, at least one subnet comprising one or more switches, a plurality of host channel adapters, and a plurality of end nodes. The method can associate the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value. The method can associate each of the one or more switches with a bitmap based P_Key table of a plurality of bitmap based P_Key tables. The method can associate each of the host channel adapters with a bitmap based P_Key table of the plurality of bitmap based P_Key tables.

A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

A logical router includes disaggregated network elements that function as a single router and that are not coupled to a common backplane. The logical router includes spine elements and leaf elements implementing a network fabric with front panel ports being defined by leaf elements. Control plane elements program the spine units and leaf to function a logical router. The control plane may define operating system interfaces mapped to front panel ports of the leaf elements and referenced by tags associated with packets traversing the logical router. Redundancy and checkpoints may be implemented for a route database implemented by the control plane elements. The logical router may include a standalone fabric and may implement label tables that are used to label packets according to egress port and path through the fabric.

System and method for supporting scalable representation of switch port status in a high performance computing environment. In accordance with an embodiment, a scalable representation of switch port status can be provided. By adding a scalable representation of switch port status at each switch (both physical and virtual)—instead of getting all switch port changes individually, the scalable representation of switch port status can combine a number of ports that can scale by just using a few bits of information for each port's status.

System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. A mapping table in DRAM can be provided through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

In one embodiment, a computer network system, includes a plurality of mesh networks, each mesh network including at least three interconnected respective internal switches with each respective internal switch being connected to each other one of the respective internal switches via a respective internal network connection, and Clos topology network connections connecting the mesh networks in a Clos topology arrangement.

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

A novel multi-stage folded Clos network and a linecard for use in a network is disclosed. The Clos network can consist of three stages, an access stage, a lower stage, and an upper stage. The access stage and the upper stage can include a plurality of switches or conventional access points. The lower stage can include a plurality of linecards. Each linecard can be made of two switch chips, each of which are connected to the ports of the linecard, and contain the same number of ports. Each switch chip can forward information in only one direction and one is used to send direction from the access stage to the upper stage, and the other from the upper stage to the access stage. The lower stage can consist of a number of sub-stages, each sub-stage can be entirely of either conventional switches or linecards. Accordingly, compared to a conventional Clos network, the provided network can increase the throughput by any power of 2 by replacing the conventional switches used in the lower stage or sub-stages with linecards.