Patent classifications
H04L49/112
CONGESTION MITIGATION IN INTERCONNECTION NETWORKS
Examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.
CONGESTION MITIGATION IN INTERCONNECTION NETWORKS
Examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.
COMPUTING SYSTEM AND DATA TRANSPORT SYSTEM
A computing system comprising: routers, configured to transport data to nodes; transport stations, configured to transport the data to the nodes through the routers; first paths, provided between adjacent ones of the routers; second paths, provided between adjacent ones of the transport stations. The computing system operates in a first mode, which transmits the data from a first target device to a second target device via the first paths and the second paths.
COMPUTING SYSTEM AND DATA TRANSPORT SYSTEM
A computing system comprising: routers, configured to transport data to nodes; transport stations, configured to transport the data to the nodes through the routers; first paths, provided between adjacent ones of the routers; second paths, provided between adjacent ones of the transport stations. The computing system operates in a first mode, which transmits the data from a first target device to a second target device via the first paths and the second paths.
HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE
An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.
HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE
An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.
COMMUNICATION CHIP AND DATA SWITCHING APPARATUS
An example communication chip includes switching dies and network processing dies connected to the switching dies. A network processing die is configured to: receive a first packet via an external port, and send a second packet via an internal port, where the second packet includes the first packet and destination information indicating a destination network processing die of the first packet. A switching die is configured to: receive the second packet, and send the second packet to a connected switching die when determining, based on the destination information, that a preset condition is not satisfied, or send the second packet to a connected first network processing die when determining that the preset condition is satisfied. The first network processing die is configured to: receive the second packet, and send the second packet to outside, or send the second packet to another network processing die.
COMMUNICATION CHIP AND DATA SWITCHING APPARATUS
An example communication chip includes switching dies and network processing dies connected to the switching dies. A network processing die is configured to: receive a first packet via an external port, and send a second packet via an internal port, where the second packet includes the first packet and destination information indicating a destination network processing die of the first packet. A switching die is configured to: receive the second packet, and send the second packet to a connected switching die when determining, based on the destination information, that a preset condition is not satisfied, or send the second packet to a connected first network processing die when determining that the preset condition is satisfied. The first network processing die is configured to: receive the second packet, and send the second packet to outside, or send the second packet to another network processing die.
Switched Protocol Transformer for High-Performance Computing (HPC) and AI Workloads
Embodiments for communicating using a switch configured to establish multiple types of communication routes. First and second upstream switch ports (USPs) communicate with first and second hosts according to first and second Compute Express Link (CXL) protocols, respectively. A downstream switch port (DSP) communicates with a device according to a third CXL protocol. The switch couples the first USP to the DSP via a first route traversing a single Virtual CXL Switch (VCS), and couples the first USP to the second USP via a second route traversing two VCSs. Optionally, the switch includes a Resource Provisioning Unit (RPU) coupling the two VCSs of the second route, terminating the first and second CXL protocols, and translating between CXL messages conforming to the first and second CXL protocols.
Switched Protocol Transformer for High-Performance Computing (HPC) and AI Workloads
Embodiments for communicating using a switch configured to establish multiple types of communication routes. First and second upstream switch ports (USPs) communicate with first and second hosts according to first and second Compute Express Link (CXL) protocols, respectively. A downstream switch port (DSP) communicates with a device according to a third CXL protocol. The switch couples the first USP to the DSP via a first route traversing a single Virtual CXL Switch (VCS), and couples the first USP to the second USP via a second route traversing two VCSs. Optionally, the switch includes a Resource Provisioning Unit (RPU) coupling the two VCSs of the second route, terminating the first and second CXL protocols, and translating between CXL messages conforming to the first and second CXL protocols.