VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. The VLSI layouts with spacial locality exploitation presented are applicable to generalized multi-stage and pyramid networks, generalized folded multi-stage and pyramid networks, generalized butterfly fat tree and pyramid networks, generalized multi-link multi-stage and pyramid networks, generalized folded multi-link multi-stage and pyramid networks, generalized multi-link butterfly fat tree and pyramid networks, generalized hypercube networks, and generalized cube connected cycles networks for speedup of s≥1. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.

A data processing apparatus includes N apparatus input ends, an input switch, K buffer areas, a first output switch, a second output switch, and M apparatus output ends. N input ends of the input switch are coupled to the N apparatus input ends, and K output ends of the input switch correspond to the K buffer areas. K.sub.1 input ends of the first output switch correspond to K.sub.1 buffer areas in the K buffer areas, and M output ends of the first output switch are coupled to the M apparatus output ends. K.sub.2 input ends of the second output switch correspond to K.sub.2 buffer areas in the K buffer areas except the K.sub.1 buffer areas, and M output ends of the second output switch are coupled to the M apparatus output ends.

This disclosure describes techniques that include selecting a member port of an aggregation bundle by evaluating utilization of paths, within a router, to member ports of an aggregation bundle. In one example, this disclosure describes a method that includes receiving network data to be output through an aggregation bundle having a plurality of member ports; identifying local member ports; identifying non-local member ports, each of the non-local member ports being reachable from the receiving line card over a path through the switch fabric to a different one of the plurality of line cards; identifying available non-local member ports by determining, for each non-local member port, whether the path through the switch fabric has low utilization; and selecting a member port by applying a hashing algorithm to a group that includes each of the identified available non-local member ports.

There is provided methods and apparatuses for transferring photonic cells or frames between a photonic switch and an electronic switch enabling a scalable data center cloud system with photonic functions transparently embedded into an electronic chassis. In various embodiments, photonic interface functions may be transparently embedded into existing switch chips (or switch cards) without changes in the line cards. The embedded photonic interface functions may provide the switch cards with the ability to interface with both existing line cards and photonic switches. In order to embed photonic interface functions without changes on the existing line cards, embodiments use two-tier buffering with a pause signalling or pause messaging scheme for managing the two-tier buffer memories.

An interconnect as a switch module (ICAS module) comprising n port groups, each port group comprising n1 interfaces, and an interconnecting network implementing a full mesh topology where each port group comprising a plurality of interfaces each connects an interface of one of the other port groups, respectively. The ICAS module may be optically or electrically implemented. According to the embodiments, the ICAS module may be used to construct a stackable switching device and a multi-unit switching device, to replace a data center fabric switch, and to build a new, high-efficient, and cost-effective data center.

This disclosure describes techniques that include selecting a member port of an aggregation bundle by evaluating utilization of paths, within a router, to member ports of an aggregation bundle. In one example, this disclosure describes a method that includes receiving network data to be output through an aggregation bundle having a plurality of member ports; identifying local member ports; identifying non-local member ports, each of the non-local member ports being reachable from the receiving line card over a path through the switch fabric to a different one of the plurality of line cards; identifying available non-local member ports by determining, for each non-local member port, whether the path through the switch fabric has low utilization; and selecting a member port by applying a hashing algorithm to a group that includes each of the identified available non-local member ports.

This disclosure describes techniques that include selecting a member port of an aggregation bundle by evaluating utilization of paths, within a router, to member ports of an aggregation bundle. In one example, this disclosure describes a method that includes receiving network data to be output through an aggregation bundle having a plurality of member ports; identifying local member ports; identifying non-local member ports, each of the non-local member ports being reachable from the receiving line card over a path through the switch fabric to a different one of the plurality of line cards; identifying available non-local member ports by determining, for each non-local member port, whether the path through the switch fabric has low utilization; and selecting a member port by applying a hashing algorithm to a group that includes each of the identified available non-local member ports.

An interconnect as a switch module (ICAS module) comprising n port groups, each port group comprising n1 interfaces, and an interconnecting network implementing a full mesh topology where each port group comprising a plurality of interfaces each connects an interface of one of the other port groups, respectively. The ICAS module may be optically or electrically implemented. According to the embodiments, the ICAS module may be used to construct a stackable switching device and a multi-unit switching device, to replace a data center fabric switch, and to build a new, high-efficient, and cost-effective data center.

One embodiment describes a network system. The system includes a primary enclosure including a network switch system that includes a plurality of physical interface ports. A first one of the plurality of physical interface ports is to communicatively couple to a network. The system further includes a sub-enclosure comprising a network interface card (NIC) to which a computer system is communicatively coupled and a downlink extension module (DEM) that is communicatively coupled with the NIC and a second one of the plurality of physical interface ports of the network switch system to provide network connectivity of the computer system to the network via the network switch system.

Embodiment provide recovering multicast data traffic during spine reload in software defined networks by identifying interfaces available between spine switches and a public network in a site; identifying Group Internet Protocol-outer (GIPo) addresses that handle multicast communications between endpoints associated together in a bridge domain, wherein the endpoints are connected via leaf switches in communication with the spine switches in a Clos topology; assigning each GIPo address to one virtual interface group (ViG) of a plurality of ViGs to generate GIPo-to-ViG mappings; distributing the GIPo-to-ViG mappings to the spine and leaf switches; assigning each ViG to one Interface as first ViG-to-Interface mappings; distributing the first ViG-to-Interface mappings to the spine and leaf switches and; when a number of available Interfaces changes, re-assigning each ViG to one currently-available Interface as second ViG-to-Interface mappings; and distributing the second ViG-to-Interface mappings to the spine switches and to the leaf switches.