Systems, methods, and devices for offloading network data to a datastore. A system includes routing chip hardware and an asynchronous object manager in communication with the routing chip hardware. The asynchronous object manager is configurable to execute instructions stored in non-transitory computer readable storage media. The instructions include asynchronously receiving a plurality of objects from one or more producers. The instructions include identifying one or more dependencies between two or more of the plurality of objects. The instructions include reordering the plurality of objects according to the one or more dependencies. The instructions include determining whether the one or more dependencies is resolve. The instructions include, in response to determining the one or more dependencies is resolved, calling back an application and providing one or more of the plurality of objects to the application.

A novel multi-stage folded Clos network and a linecard for use in a network is disclosed. The Clos network can consist of three stages, an access stage, a lower stage, and an upper stage. The access stage and the upper stage can include a plurality of switches or conventional access points. The lower stage can include a plurality of linecards. Each linecard can be made of two switch chips, each of which are connected to the ports of the linecard, and contain the same number of ports. Each switch chip can forward information in only one direction and one is used to send direction from the access stage to the upper stage, and the other from the upper stage to the access stage. The lower stage can consist of a number of sub-stages, each sub-stage can be entirely of either conventional switches or linecards. Accordingly, compared to a conventional Clos network, the provided network can increase the throughput by any power of 2 by replacing the conventional switches used in the lower stage or sub-stages with linecards.

A N×M non-blocking switch matrix, where N and M are integers, includes an input stage having a plurality of m/2-way multiport switches, where quotient m/2 is a positive integer less than M, and an output stage having a plurality of n/2-way multiport switches, where quotient n/2 is a positive integer less than N. The switch matrix further includes a transfer stage having a plurality of transfer switches operatively connected between the input stage and output stage, and selectively applying outputs of the m/2-way multiport switches to inputs of the n/2-way multiport switches such that any given input to the m/2-way multiport switches is connectable to any given output of the n/2-way multiport switches.

In one embodiment, a computer network system, includes at least one lower tier of lower switches, at least one upper tier of upper switches, and a middle tier of middle switches connected down-tier to ones of the lower switches and up-tier to ones of the upper switches, one of the middle switches including a clos topology arrangement of leaf and spine switches, the leaf switches being connected via K internal network connections to the spine switches, each leaf switch being connected to each spine switch, the leaf switches being connected via N down-tier network connections to ones of the lower switches and via M up-tier network connections to ones of the upper switches, there being more of the N down-tier network connections than there are of the M up-tier network connections, and there being less of the K internal network connections than there are of the N and M connections.

A network segment route and a host route are advertised to a Spine node; the network segment route advertised by the Spine node is learned; when a first packet hits the network segment route, the first packet is sent to a Spine node corresponding to a next hop of the hit network segment routes so that the Spine node sends the first packet to a Leaf node corresponding to a next hop of a host route hit by the first packet.

A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.

A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.

Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ shuffle exchange links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block.

Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ shuffle exchange links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block.

A network device receives multi-destination packets from a first node and forwards at least a first of the multi-destination packets to another network device using a first multi-destination tree with respect to the network device. The network device detects that a link associated with the first multi-destination tree satisfies one or more criteria and, in response to detecting that the link satisfies the one or more criteria, selects a second multi-destination tree with respect to the network device. The network device forwards at least a second of the multi-destination packets to the other network device using the second multi-destination tree.