A method is provided of detecting packet error during a transmission of a flit along a path from a source node through one or more intermediate nodes to a destination node. The method includes identifying a stalled node, from among the source and intermediate nodes, which prevents the transmission of the flit. The method includes generating, by a transmitter of the stalled node, a CRC for the flit and placing the CRC in an IDLE pattern of the flit. The method includes checking, by a receiver of an intermediate node subsequent to the stalled node, the CRC for the flit. The method includes sending, by a transmitter of the intermediate node, an error code to the destination node, and releasing the nodes from the intermediate node to and including the destination node, responsive to a detection, by the intermediate node, of an error in the CRC for the flit.

A network device, such as a network switch, can include an ingress to receive data packets from a network. The ingress can communicate with an egress included in the network device though a fabric included in the network device. At least one of ingress and the egress can enqueue a data packet prior to receipt of all cells of the data packet. The ingress can also commence with dequeue of the cells of the received data packet prior to receipt of the entire data packet from the network. At least one of ingress and the egress can process the data packets using cut-through processing and store-and-forward processing. In a case of cut-through processing of a data packet at both the ingress and the egress of a network device, such as CIOQ switch, the fabric can be allocated to provide a prioritized virtual channel through the fabric for the data packet.

The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.

In a method for processing packets in a network device, a first packet is received at a first port of the network device. A first set of bits, corresponding to a first set of bit locations in a header of the first packet, is extracted from the header of the first packet. A first set of processing operations is performed to process the first packet using the first set of bits. A second packet is received at a second port of the network device. A second set of bits, corresponding to a second set of bit locations in a header of the second packet, is extracted from the header of the second packet. A second set of processing operations is performed to process the second packet using the second set of bits.