A communications device that includes a requester and a responder may support multiple transaction classes, including an ordered transaction class, while maintaining a bifurcated requester/responder architecture. Before a responder has a non-posted transaction response to transmit on an interconnect, it receives an indication from the requester that there is not a pending posted transaction on the interconnect.

Systems and methods for routing communication among a plurality of devices are described. In an example, a controller can detect a communication initiated from a first device to a target device among a second device and a third device. The controller can identify the second device as the target device. The controller can, in response to identifying the second device as the target device, activate a direct communication path between the first device and the second device to allow the first device to communicate with the second device using direct communication mode. The controller can, in response to identifying the second device as the target device, activate redriver path between the first device and the third device to allow the first device to communicate with the third device using redriver mode.

System and method for aggressive credit waiting in a high performance computing environment. In accordance with an embodiment, systems and methods can provide for an indexed matrix of credit wait policies between ports within a single switch. In addition, systems and methods can provide for an array of credit wait polices at an egress port from a switch, the array being indexed by virtual lane.

System and method for aggressive credit waiting in a high performance computing environment. In accordance with an embodiment, systems and methods can provide for an indexed matrix of credit wait policies between ports within a single switch. In addition, systems and methods can provide for an array of credit wait polices at an egress port from a switch, the array being indexed by virtual lane.

Embodiments of the present disclosure are directed to protocol state transition and/or resource state transition tracker configured to monitor, e.g., via filters, for certain protocol state transitions/changes or host hardware resource transitions/changes when a host processor in the control plane that performs such monitoring functions is unavailable or overloaded. The filters, in some embodiments, are pre-computed/computed by the host processor and transmitted to the protocol state transition and/or resource state transition tracker. The protocol state transition and/or resource state transition tracker may be used to implement a fast upgrade operation as well as load sharing and or load balancing operation with control plane associated components.

Technologies for adaptive network packet egress scheduling include a switch configured to configure an eligibility table for a plurality of ports of the switch, wherein the eligibility table includes a plurality of rounds. The switch is further configured to retrieve an eligible mask corresponding to a round of a plurality of rounds of the eligibility table presently being scheduled and determine a ready mask that indicates a ready status of each port. The switch is further configured to determine, for each port, whether the eligible status and the ready status indicate that port is both eligible and ready, and schedule, in response to a determination that at least one port has been determined to be both eligible and ready, each of the at least one port that has been determined to be both eligible and ready. Additional embodiments are described herein.

Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

A transmission device (10) includes a flow table (11) that stores identification information about an uninterruptible target flow; a transmission-side identification unit (12) that identifies whether a received packet is from the target flow or a non-target flow based on whether the received packet matches the identification information about the target flow stored in the flow table (11); a tag application unit (13) that applies, to packets from the target flow, an uninterruptible identifier indicating that the packets are from the target flow and a sequence number for distinguishing the packets from other packets; and a branch unit (14) that branches the packets from the target flow processed by the tag application unit (13) into packets to be transferred to an active path (41) among redundant routes and packets to be transferred to a backup path (42) among the redundant routes.

An automatic test device is disclosed. The automatic test device is includes connection ports, a processor, and a transmission integrated interface. The connection ports is configured to couple to a device under test. The processor is coupled to the connection ports and is configured to transmit a test instruction through the connection ports to the device under test. The device under test is in a test mode after receiving the test instruction, and the first processor is configured to receive a test signal transmitted through the connection ports from the device under test when the device under test is in the test mode. The transmission integrated interface is coupled between the connection ports and the processor, and is configured to transmit at least one of the test instructions to the connection ports or the processor. An automatic test system is also disclosed herein.