Patent classifications
H04L49/3036
COMBINED INPUT AND OUTPUT QUEUE FOR PACKET FORWARDING IN NETWORK DEVICES
An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.
Apparatuses and methods involving managing port-address assignments
An example apparatus for a local area network. The apparatus includes, at one of a plurality of logic nodes, a plurality of ports and a plurality of shared registers. The plurality of shared registers have a port address table to provide configurable port-address assignments that identify respective ones of the plurality of ports. The apparatus further includes a management interface controller that communicates with the plurality of ports and accesses at least one register via a selected one of the ports, and in response configures or manages the port-address assignments within the port address table.
Use of stashing buffers to improve the efficiency of crossbar switches
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
QUEUE SCHEDULER CONTROL VIA PACKET DATA
Some embodiments provide a method for a hardware forwarding element that includes multiple queues. The method receives a packet at a multi-stage processing pipeline of the hardware forwarding element. The method determines, at one of the stages of the processing pipeline, to modify a setting of a particular one of the queues. The method stores an identifier for the particular queue and instructions to modify the queue setting with data passed through the processing pipeline for the packet. The stored information is subsequently used by the hardware forwarding element to modify the queue setting.
QUEUE PROTECTION USING A SHARED GLOBAL MEMORY RESERVE
The subject technology relates to the management of a shared buffer memory in a network switch. Systems, methods, and machine readable media are provided for receiving a data packet at a first network queue from among a plurality of network queues, determining if a fill level of a queue in a shared buffer of the network switch exceeds a dynamic queue threshold, and in an event that the fill level of the shared buffer exceeds the dynamic queue threshold, determining if a fill level of the first network queue is less than a static queue minimum threshold.
Distributed artificial intelligence extension modules for network switches
Distributed machine learning systems and other distributed computing systems are improved by compute logic embedded in extension modules coupled directly to network switches. The compute logic performs collective actions, such as reduction operations, on gradients or other compute data processed by the nodes of the system. The reduction operations may include, for instance, summation, averaging, bitwise operations, and so forth. In this manner, the extension modules may take over some or all of the processing of the distributed system during the collective phase. An inline version of the module sits between a switch and the network. Data units carrying compute data are intercepted and processed using the compute logic, while other data units pass through the module transparently to or from the switch. Multiple modules may be connected to the switch, each coupled to a different group of nodes, and sharing intermediate results. A sidecar version is also described.
APPARATUSES AND METHODS INVOLVING MANAGING PORT-ADDRESS ASSIGNMENTS
An example apparatus for a local area network. The apparatus includes, at one of a plurality of logic nodes, a plurality of ports and a plurality of shared registers. The plurality of shared registers have a port address table to provide configurable port-address assignments that identify respective ones of the plurality of ports. The apparatus further includes a management interface controller that communicates with the plurality of ports and accesses at least one register via a selected one of the ports, and in response configures or manages the port-address assignments within the port address table.
Queue scheduler control via packet data
Some embodiments provide a method for a hardware forwarding element that includes multiple queues. The method receives a packet at a multi-stage processing pipeline of the hardware forwarding element. The method determines, at one of the stages of the processing pipeline, to modify a setting of a particular one of the queues. The method stores an identifier for the particular queue and instructions to modify the queue setting with data passed through the processing pipeline for the packet. The stored information is subsequently used by the hardware forwarding element to modify the queue setting.
Method and system for improving switching capacity of software-based switches in access networks
This disclosure relates to a method of improving switching capacity in a software-based network switch. The method may involve storing a data packet in a first local buffer, storing one or more header fields of the data packet in a second local buffer. A common identifier may be assigned to the data packet stored in the first local buffer and the one or more header fields stored in the second local buffer. The one or more header fields may be directly sent from the NIC to the CPU for the data packet processing. At least one header field of the one or more header fields may be modified by the CPU. Further, the one or more header fields may be overwritten with the at least one modified header field in the data packet stored in the first local buffer of the NIC based on the common identifier.
PRIORITY-BASED FLOW CONTROL
Some embodiments provide a method for a hardware forwarding element. The method adds a received packet to a buffer. The method determines whether adding the packet to the buffer causes the buffer to pass one of multiple flow control thresholds, each of which corresponds to a different packet priority. When adding the packet to the buffer causes the buffer to pass a particular flow control threshold corresponding to a particular priority, the method generates a flow control message for the particular priority.