Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.

The present subject matter relates generally to optimization of distribution of data packets in a High Performance Computing (HPC) switch. The HPC switch receives data packets from controllers communicatively connected to HPC switch, through interconnected Queue Pair (QP) lanes and assigns a destination virtual lane (VL) for each data packet based on service level information. Further, the HPC switch generates plurality of clusters of ports that are coupled with each interconnected VL based on latency determined dynamically for each port. Finally, the HPC switch transmits a first group of data packets through ports belonging to a primary cluster of plurality of clusters and transmits acknowledgement key-packet associated with second group of data packets through the ports belonging to secondary clusters of plurality of clusters, based on destination VL assigned for each data packet to other controllers for optimizing the distribution of the plurality of data packets in the HPC switch.

Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

The present subject matter relates generally to optimization of distribution of data packets in a High Performance Computing (HPC) switch. The HPC switch receives data packets from controllers communicatively connected to HPC switch, through interconnected Queue Pair (QP) lanes and assigns a destination virtual lane (VL) for each data packet based on service level information. Further, the HPC switch generates plurality of clusters of ports that are coupled with each interconnected VL based on latency determined dynamically for each port. Finally, the HPC switch transmits a first group of data packets through ports belonging to a primary cluster of plurality of clusters and transmits acknowledgement key-packet associated with second group of data packets through the ports belonging to secondary clusters of plurality of clusters, based on destination VL assigned for each data packet to other controllers for optimizing the distribution of the plurality of data packets in the HPC switch.

A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.

Some embodiments provide a method for scheduling a packet to be dequeued to a processing pipeline of a hardware forwarding element. The method selects a node representing one of multiple ports associated with the processing pipeline. For each of one or more layers of logical queues, the method (i) identifies a set of logical queue nodes associated with a previously selected node based on a configuration that maps multiple physical queues to the multiple ports via the one or more layers of logical queues and (ii) selects one of the identified logical queue nodes based on properties of the identified logical queue nodes. The method selects one of a set of physical queues associated with a selected logical queue node of the last layer of logical queues. The method dequeues a next packet from the selected physical queue for processing by the processing pipeline.

A multi-processor computing system comprising a second processing device to generate outgoing data packets and comprising a second network stack to save the outgoing data packets in a second outgoing packet buffer of the second processing device. A second network driver to save an outgoing buffer pointer in a second transmission ring of the second processing device, the outgoing buffer pointer corresponding to the second outgoing packet buffer. A first processing device comprising a first network driver to move the outgoing buffer pointer from the second transmission ring to a send ring in the first processing device. A network interface controller (NIC) to obtain the outgoing buffer pointer from the send ring. The NIC to copy the outgoing data packets from the second outgoing packet buffer to a transmission queue of the NIC. The NIC to transmit the outgoing data packets to another computing system over a communication network.

Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

A luminaire having a waveguide suspended beneath a mounting element, the waveguide has a first surface proximal to the mounting element, a second surface distal to the mounting element, and an edge between the first and the second surfaces. At least one cavity extends into the waveguide from the first surface to the second surface. A LED component is coupled to the waveguide so as to emit light into the cavity. LED support structures are also disclosed.

A network switch includes a buffer to store network packets linked to queues to feed the packets to output ports of the switch associated with the queues. The buffer is shared dynamically among multiple traffic pools. The network switch determines per-pool dynamic thresholds each based on an amount of unused buffer space, and per-queue dynamic thresholds based on amounts of unused buffer space available in the pools with which the queues are associated. The network switch receives packets, and for each received packet, the network switch admits the packet to the pool with which the packet is associated and the queue for which the packet is destined if (i) occupancy of the associated pool is less than the corresponding per-pool dynamic threshold, and (ii) occupancy of the queue for which the packet is destined is less than the corresponding per-queue dynamic threshold, and otherwise drops the packet.