Patent classifications
H04L49/3045
Low latency flow control in data centers
A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.
System and method for supporting efficient virtual output queue (VOQ) packet flushing scheme in a networking device
A system and method can support packet switching in a network environment. The system can include an ingress buffer on a networking device, wherein the ingress buffer, which includes one or more virtual output queues, operate to store one or more incoming packets that are received at an input port on the networking device. Furthermore, the system can include a packet flush engine, which is associated with the ingress buffer, wherein said packet flush engine operates to flush a packet that is stored in a said virtual output queue in the ingress buffer, and notify one or more output schedulers that the packet is flushed, wherein each output scheduler is associated with an output port.
Virtual memory protocol segmentation offloading
Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, presence of outbound payload data, distributed across a first and second payload buffer, within a user memory space of a network device that has been generated by a user process is determined by a bus/memory interface or a network interface unit. The payload data is fetched by performing direct virtual memory addressing of the user memory space including mapping virtual addresses of the payload buffers to corresponding physical addresses, including: (i) when the payload buffers are noncontiguous, then retrieving the outbound payload data with reference to multiple buffer descriptors having starting virtual addresses of the payload buffers and (ii) when they are contiguous, then retrieving the outbound payload data with reference to a single buffer descriptor. The outbound payload data is then segmented across one or more TCP packets.
Configurable network-on-chip for a programmable device
An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
Networking system having multiple components with multiple loci of control
Each switch unit in a networking system shares its local state information among other switch units in the networking system, collectively referred to as the shared forwarding state. Each switch unit creates a respective set of output queues that correspond to ports on other switch unites based on the shared forwarding state. A received packet on an ingress switch unit operating in accordance with a first routing protocol instance can be enqueued on an output queue in the ingress switch; the packet is subsequently processed by the egress switch unit, operating in accordance with a second routing protocol instance that corresponds to the output queue.
Mapped FIFO buffering
A network interface device for connection between a network and a data processing system, the network interface device comprising: a plurality of ports for receiving data packets directed to the data processing system. An interface services the ports in a predetermined order and writes the data packets to buffers of a common memory. Each buffer is part of one of a set of linked logical sequence of buffers forming virtual queues in the common memory. Each virtual queue is associated with a port. A memory manager selects buffers of the common memory so as to cause the interface to populate the plurality of virtual queues with data packets.
Packet Forwarding Method and Apparatus
Embodiments of the present invention disclose a packet forwarding method and apparatus. The method includes: receiving, by a first scheduler, a target packet; sending the target packet to a destination physical egress port corresponding to the egress port information, and increasing, according to the queue identifier, a queue length of a virtual queue corresponding to the queue identifier by the packet length; sending update information to a second scheduler, where the update information includes that the queue length of the virtual queue is increased by the packet length; and decreasing the queue length of the virtual queue by the packet length according to a bandwidth scheduling result that is corresponding to the update information and sent by the second scheduler. In this way, even if back pressure appears in the destination physical egress port corresponding to the target packet, that the first scheduler sends the target packet is not affected.
Crossbar switch and recursive scheduling
A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue (XQ), which can store one or more packets to be routed. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements a shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the row scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughput with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.
Signalling congestion
Congestion in respect to a network element operable to forward data items in a telecommunications networks, and in respect to a processing element operable to process requests for service is signaled. In either, the element is operable to perform its processing function at up to a processing rate which is subject to variation, and has a queue for items awaiting processing having a counter associated therewith which maintains a count from which a queue metric is derivable. A method comprises: updating the count at a rate dependent on the processing rate; further updating the count in response to receipt of items awaiting processing; and signalling a measure of congestion in respect of the element in dependence on the queue metric; then altering the rate at which the count is being updated and adjusting the counter whereby to cause a change in the queue metric if the processing rate has changed.
Virtual network device
A virtual network device increases the effective number of local physical ports by converting each of the local physical ports into a plurality of virtual local physical ports, and the effective number of network physical ports by converting each of the network physical ports into a plurality of virtual network physical ports.