A parallel scheduling apparatus includes an information managing unit generating a first request information for scheduling, a first scheduling unit performing first scheduling and then generating first matching information on the basis of the first request information, and a second scheduling unit performing second scheduling on the basis of the first request information and the first matching information. The parallel scheduling has an advantage of improving the scheduling performance and lowering the implementation complexity, ensuring low delay and transmission fairness among VOQs at low input traffic, being applied to all scheduling algorithms that perform existing multi-iterations, and providing efficient scheduling in a packet switch having a long RTT time or having a very short time slot or cell size, such as an optical switch.

Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array (FPGA) that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.

A network switch is capable of supporting cut-through switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum, which may aggregate multiple packets, and which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum (MoR) state to support cut-through. The fabric scheduler performs a multi-stage scheduling process to progressively narrow the selection of requests, including stages of arbitration in virtual output port level, virtual output port group level, tile level, egress port level, and port group level. Each tile receives the grants for its requests and accordingly sends request data to a switch fabric for transmission to the destination egress ports.

Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.

A networking adaptor and method of transferring data are depicted and described herein. One example of the networking adaptor is provided with a host interface and a network interface. The network interface may include a transmit portion and a receive portion. The transmit portion may include a first set of data paths and the receive portion may include a second set of data paths. Both the first set of data paths and second set of data paths are configurable to be aggregated or de-aggregated to support a single port operation that represents a combined bandwidth of the data paths in the first set of data paths or the second set of data paths.

A system and method for routing network packets. A switch fabric connects a plurality of forwarding units, including an egress forwarding unit and two or more ingress forwarding units, each ingress forwarding unit forwarding network packets to the egress forwarding unit via the switch fabric. The egress forwarding unit includes a scheduler and an output queue. Each ingress forwarding unit includes a Virtual Output Queue (VOQ) connected to the output queue and a VOQ manager. The scheduler receives time of arrival information for network packets stored in the VOQs, determines, based on the time of arrival information for each network packet, a device resident time for the network packets stored in the VOQs, and requests, from one of the VOQs and based on the device resident times, the network packet with the longest device resident time.

The present invention provides a circuit within a switch, wherein the circuit includes a memory and a control circuit. The memory includes at least a first area and a second area, the first area is used to provide a minimum guaranteed storage space for each of a plurality of egress queues, the second area is used to provide a shared space of the plurality of egress queues. The control circuit is coupled to the memory, and when an input port of the switch receives an input packet and stores the input packet into the memory, the control circuit dynamically determines a size of the second area according to a number of the egress queues that the input packet is forwarded to.

At a server, a load monitoring unit monitors whether or not a predetermined condition regarding processing of requests is satisfied. In the case where the predetermined condition is not satisfied, a wait-time calculating unit calculates a wait time as a time parameter for controlling the speed of time flow at a player terminal side. A request executing unit executes requests in the order of arrival and generates responses. A response sending control unit executes control to send responses to the player terminals that have sent the corresponding requests and to also send to the player terminals information representing the wait time in the case where the wait time has been calculated.

Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.

A network switch capable of supporting cut-though switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum which may aggregate multiple packets, which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum (MoR) state to support cut-through. The fabric scheduler performs a multi-stage scheduling process to progressively narrow the selection of requests, including stages of arbitration in virtual output port level, virtual output port group level, tile level, egress port level and port group level. Each tile receives the grants for its requests and accordingly sends request data to a switch fabric for transmission to the destination egress ports.