H04L49/3063

Method and apparatus to optimize multi-destination traffic over etherchannel in stackwise virtual topology

Methods and systems are disclosed. The method comprises: designating a first plurality of links from a first stack segment to a second stack segment as a first etherchannel link; designating a second plurality of links from the first stack segment to a third stack segment as a second etherchannel link, where the second stack segment and the third stack segment are in communication with a fourth stack segment; designating the first etherchannel link and the second etherchannel link as members of a hierarchical etherchannel link; and sending a packet from the first stack segment to the fourth stack segment using the hierarchical etherchannel link.

PACKET PROCESSING WITH PER FLOW HASH KEY SELECTION
20230055703 · 2023-02-23 ·

An apparatus is described. The apparatus includes queue assignment circuitry. The queue assignment circuitry includes first circuitry to select amongst multiple hash keys and second circuitry to hash content of a packet's header with a selected one of the hash keys.

Stateful processing unit with min/max capability

Some embodiments provide a network forwarding integrated circuit (IC) that includes at least one packet processing pipeline. The packet processing pipeline includes multiple match-action stages, at least one of which includes a stateful processing unit that operates at a line rate of the network forwarding IC. The stateful processing unit is configured to receive data stored in a memory location associated with a stateful table of the match-action stage. The data includes a set of values. The stateful processing unit is further configured to identify one of a maximum value and a minimum value from the set of values, and to output the identified value for use by a next match-action stage.

Method and Apparatus to Optimize Multi-Destination Traffic Over Etherchannel in Stackwise Virtual Topology

Methods and systems are disclosed. The method comprises: designating a first plurality of links from a first stack segment to a second stack segment as a first etherchannel link; designating a second plurality of links from the first stack segment to a third stack segment as a second etherchannel link, where the second stack segment and the third stack segment are in communication with a fourth stack segment; designating the first etherchannel link and the second etherchannel link as members of a hierarchical etherchannel link; and sending a packet from the first stack segment to the fourth stack segment using the hierarchical etherchannel link.

Adaptive private network (APN) bandwidth enhancements

Techniques are described to automatically activate and deactivate standby backup paths in response to changing bandwidth requirements in an adaptive private network (APN). The APN includes one or more regular active wide area network (WAN) links in an active mode and an on-demand WAN link in a standby mode. The on-demand WAN link is activated to supplement the conduit bandwidth when an available bandwidth of the conduit falls below a pre-specified trigger bandwidth threshold and the conduit bandwidth usage exceeds a usage threshold of a bandwidth of the conduit that is being supplied by the active paths (BWc). The on-demand WAN link is deactivated to standby mode when an available bandwidth of the conduit is above the pre-specified trigger bandwidth threshold and the conduit bandwidth usage drops below the usage threshold of BWc techniques for adaptive and active bandwidth testing of WAN links in an APN are also described.

Method and system for classifying data packet fields on FPGA
11489753 · 2022-11-01 · ·

A method and system for classifying data packet fields are disclosed. They associate a final tag to each of the fields in a data packet in relation to a set of classifying rules, and involve building a decision tree using a recursive algorithm to apply the set of classifying rules on the data packet fields, mapping each node of the built decision tree respectively to a processing element of a FPGA, each processing element comprising a processor and a memory, pipelining all mapped processing elements, and processing the data packet fields through the pipelined and mapped processing elements.

Messaging between remote controller and forwarding element

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

User interface for customizing data streams

Systems and methods are described for customizable data streams in a streaming data processing system. Routing criteria for the customizable data streams are defined by a user, an automated process, or any other process. The routing criteria can be defined using graphical controls. The streaming data processing system uses the routing criteria to determine data that should be used to populate a particular data stream. Further, processing pipelines are customized such that a particular processing pipeline can obtain data from a particular user defined data stream and write data to a particular user defined data stream. Data is routed through the user defined data streams and customized processing pipelines based on a data route. A data route for a set of data may include multiple user defined data streams and multiple processing pipelines. The data route can include a loop of processing pipelines and data streams.

Techniques for instruction perturbation for improved device security

Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.

Off-Chip Memory Backed Reliable Transport Connection Cache Hardware Architecture

An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.