H04L49/355

APPLICATION DATA FLOW GRAPH EXECUTION USING NETWORK-ON-CHIP OVERLAY

Methods and systems for the for executing an application data flow graph using a network of computational nodes are disclosed. In specific examples, the network of computational nodes can be a network-on-chip for a multicore processor. One method includes transitioning first application data from a first source computational node to an intermediary computational node. The method can also include providing second application data, from a computation layer of the network of computational nodes, on the intermediary computational node. The method can also include multicasting the first application data in combination with the second application data from the intermediary computational node to at least two destination computational nodes. The first source computational node, the intermediary computational node, and the at least two destination computational nodes are all in the network of computational nodes.

Small form factor pluggable unit with wireless capabilities and methods, systems and devices utilizing same
11388091 · 2022-07-12 ·

The present subject matter relates to one or more devices, systems and/or methods for providing wireless telecommunication services. A Small Form Factor Pluggable Unit (SFP) incorporates wireless capabilities, and includes an integrated or an external antenna. The SFP comprises wireless circuitry for transmitting and receive multiple and distinct wireless signals, including Wi-Fi and Bluetooth for communicating with various equipment, devices and/or networks.

Circuitry for demarcation devices and methods utilizing same
11444870 · 2022-09-13 ·

The present subject matter relates to methods, systems, devices, circuitry and equipment providing for communication service to be transported between first and second networks, and which monitors the communication service and/or injects test signals, and which can provide redundancy. At least one demarcation point or line is established between the first network and the second network, and/or between the first network, the second network and/or a third network. The Circuitry comprises a plurality of input amplifiers, output amplifiers, and multiplexer switches between a plurality of Port connectors. An SFP module or a WSFP module is inserted in the Ports.

ON-BOX BEHAVIOR-BASED TRAFFIC CLASSIFICATION

In one embodiment, a networking device in a network detects an traffic flow conveyed in the network via the networking device. The networking device generates flow data for the traffic flow. The networking device performs a classification of the traffic flow using the flow data as input to a machine learning-based classifier. The networking device performs a mediation action based on the classification of the traffic flow.

On-box behavior-based traffic classification

In one embodiment, a networking device in a network detects an traffic flow conveyed in the network via the networking device. The networking device generates flow data for the traffic flow. The networking device performs a classification of the traffic flow using the flow data as input to a machine learning-based classifier. The networking device performs a mediation action based on the classification of the traffic flow.

Multi-functional device for communications networks and methods and systems utilizing same
11283710 · 2022-03-22 ·

The present subject matter relates to methods, circuitry and equipment providing a multi-functional, cost effective, media independent, open platform device for communication services using differential signaling interfaces. The methods, circuitry and equipment comprise a plurality of input amplifiers, output amplifiers, and retimers. A non-blocking cross-point switch may be used to switch any differential signals from the cross-point switch input to output. The device aggregates communication services from a plurality of lower service capacity connectors and interfaces to a single higher capacity connector and interfaces. The device can establish a demarcation point with a single device capable of supporting any communication services, any physical media interfaces, from any location.

Daisy-chained synchronous ethernet clock recovery

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

TECHNIQUES FOR HANDLING MESSAGE QUEUES
20210226903 · 2021-07-22 ·

Techniques are disclosed relating to handling queues. A server-based platform, in some embodiments, accesses queue information that includes performance attributes for a plurality of queues storing one or more messages corresponding to one or more applications. In some embodiments, the platform assigns, based on the performance attributes, a corresponding set of the plurality of queues to each of a plurality of processing nodes of the platform. In some embodiments, the assigning of a corresponding set of queues to a given one of the plurality of processing nodes causes instantiation of: a first set of one or more dequeuing threads and a second set of one or more processing threads. The dequeuing threads may be executable to dequeue one or more messages stored in the corresponding set of queues. The processing threads may be executable to perform one or more tasks specified in the dequeued one or more messages.

Apparatus and packet processing method
11082335 · 2021-08-03 · ·

The method is applied to an SDN network, where the SDN network includes one target computing apparatus and a plurality of openflow switches. The target computing apparatus communicates with the plurality of openflow switches. The method includes: receiving, by the target computing apparatus, a first bridge protocol data unit (BPDU) packet sent by a first openflow switch, where the first BPDU packet carries a device identifier and a port identifier; generating, by the target computing apparatus, a feedback packet based on the first BPDU packet, where the feedback packet includes spanning tree protocol information of a conventional switching device, and carries the port identifier; and sending, by the target computing apparatus, the feedback packet to the first openflow switch based on the device identifier.

NOC RELAXED WRITE ORDER SCHEME
20210303508 · 2021-09-30 ·

Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.