H04L49/405

Switch, switching system, switching network chip component, and forwarding chip component

Disclosed are a switch, a switching system, a switching network chip component, and a forwarding chip component. The switch includes: a switching network chip component packaged as an independent device, a forwarding chip component packaged as an independent device, and a controller. The switching system includes at least one switch and at least two network devices connected to the switch. The switching network chip component includes: a first cartridge housing, a switching network chip, a first heat dissipation component, and a first power supply component arranged inside the first cartridge housing. The forwarding chip component includes: a second cartridge housing, a forwarding chip, a second heat dissipation component, and a second power supply component arranged inside the second cartridge housing.

METHOD AND APPARATUS FOR SUPRESSING ELECTROMAGNETIC INTERFERENCE
20170163571 · 2017-06-08 ·

A method and an apparatus for suppressing electromagnetic interference are disclosed. The method includes: receiving a signal from an IC end and performing common-mode suppression processing on the received signal, to at least eliminate or mitigate an interference signal mixed in the received signal and performing coupling processing on the signal on which common-mode suppression processing has been performed, to at least obtain a signal having an enhanced driving capability, and sending the signal to a network interface end. According to embodiments of the present disclosure, because first a signal from an IC end is received and common-mode suppression processing is performed on the received signal, at least an interference signal is eliminated or mitigated in advance; next, coupling processing is then performed on the signal on which common-mode suppression processing has been performed, to at least obtain a signal having an enhanced driving capability, and the signal is sent to the network interface end.

METHOD TO ENABLE INTEL MINI-MEZZ OPEN COMPUTE PROJECT (OCP) PLUG-AND-PLAY NETWORK PHY CARDS

Methods for implementing mini-mezzanine Open Compute Project (OCP) plug-and-play Network PHY Cards and associated apparatus. In accordance with one aspect, the MAC (Media Access Channel) and PHY (Physical) layer functions in one or more communication protocol stacks are split between a MAC block in a Platform Controller Hub (PCH) or processor SoC and a PHY card installed in a mezzanine slot of a platform and including one or more ports. During platform initialization operations, configuration parameters are read from the PHY card including a PHY card ID, and a corresponding configuration script is selected and executed to configure the PHY card for use in the platform. The configuration parameters are also used to enumerate PCIe devices associated with physical functions and ports supported by the PHY card.

Scheme for addressing protocol frames to target devices

Addressing a frame to a target device, the frame being one of a protocol that defines the frame with at least an address part and a payload data part, including obtaining an address of the target device, splitting the address into a first part and a second part, allocating the first part in the address part of the frame, and allocating the second part in the payload data part of the frame.

Avionics calculator with integrated routing module, related communication network and communication installation, and aircraft comprising such a communication installation
20170078142 · 2017-03-16 ·

This avionic calculator, intended to be loaded on board an aircraft, the avionic calculator includes a protective casing and at least one module from among an information processing module able to execute at least one software application, an input/output management module and an electric power supply management module, each module being positioned inside the casing. The avionic calculator further includes a routing module positioned inside the casing, the routing module including several communication ports and being configured for transmitting at least one message from an input communication port to an output communication port.

Pre-charge buffer for analog-to-digital converter

A pre-charge buffer for sampling input signals and generating a sampled output signal includes a coarse sampling circuit, a fine sampling circuit, and a sample and hold circuit. The coarse sampling circuit pre-samples the input signals during hold phases and for a first predetermined time interval during sample phases of the corresponding sample and hold cycles, and generates a first output signal. The fine sampling circuit samples the input signals during sample phases and generates a second output signal. The sample and hold circuit receives the first and second output signals, and generates a sampled output signal. The coarse sampling circuit provides the first output signal for a predefined time interval during the sample phases to reduce the effect of charge injection and charge sharing. The system uses bottom plate sampling to reduce charge injection caused by switches in the coarse sampling circuit.

Input current cancellation scheme for fast channel switching systems

A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

FLEXIBLE ETHERNET CHIP-TO-CHIP INTEFACE SYSTEMS AND METHODS
20170006360 · 2017-01-05 ·

A Chip-to-Chip (C2C) interface utilizing Flexible Ethernet (FlexE) includes circuitry configured to provide a packet interface on a single card or over backplane/fabric links between two devices, wherein the circuitry comprises flow control and channelization for the FlexE. Each of the two devices can include any of a Network Processor (NPU), a Fabric Interface Card (FIC), a framer, and a mapper. A rate of the FlexE can be increased to support additional information for the flow control and the channelization.

SECURE IDENTIFICATION OF AIR-GAPPED NETWORKS USING ONE-WAY COMMUNICATION

Disclosed herein are receive-only network devices and methods for use for securely identifying a network. The receive-only network device comprised a network physical layer (PHY) circuit configured to establish a physical layer connection to a network via one or more wired transmission mediums and a controller electrically coupled to a receive channel of the PHY via a unidirectional hardware buffer configured to transfer electronic signals received from the PHY and block electronic signals received from the controller. The controller is configured to receive from the PHY one or more link layer frames transmitted by one or more network controllers of the network and intercepted by the PHY, extract one or more network attributes of the network from the one or more intercepted link layer frames, identify the network at least partially according to the one or more extracted network attributes, and present the identity of the network to a user.

NETWORKING SUBSYSTEM/SWITCH DEVICE CONNECTION CONFIGURATION SYSTEM
20250274405 · 2025-08-28 ·

A networking subsystem/switch device connection configuration system includes a switch device having a switch physical port, and an endpoint device including a networking subsystem having a plurality of networking physical ports. The networking subsystem detects connection of respective cable connectors to each of the plurality of networking physical ports. If the networking subsystem determines that each of the respective cable connectors connected to the plurality of networking physical ports are included on the same cable, it configures a single networking logical port to transmit data between each of the plurality of networking physical ports and the switch physical port.