H04L49/501

Coordinated congestion control in network-attached devices

A device is described. The device may include a network port to connect to a network. The device may include a first controller configured to send and receive a first communication across the network using the network port. The device may include storage for a controller record for the controller may store a congestion score, a congestion timestamp, and an uncongested timestamp. The device may also include storage for a device-wide record including at least a second congestion score and a second congestion timestamp for the first controller and a third congestion score and a third congestion timestamp for a second controller. The device-wide record may be based at least in part on the controller record. A throttle may limit a second communication of a second controller based at least in part on the device-wide record.

Time-division multiplexing scheduler and scheduling device

A time-division multiplexing (TDM) scheduler determines a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.

Time-division multiplexing scheduler and scheduling device

Disclosed is a time-division multiplexing (TDM) scheduler capable of determining a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.

DYNAMICALLY RECONFIGURING DATA PLANE OF FORWARDING ELEMENT TO ACCOUNT FOR POWER CONSUMPTION
20230388184 · 2023-11-30 · ·

Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state.

REVIEW AND RETRY FOR MINIMUM SPEED PORT CHANNEL
20230027800 · 2023-01-26 ·

A review and retry mechanism ensures a port channel can be configured to provide and maintain a minimum data speed. A timer-based review sequence reviews the constituent interfaces of a port channel to determine if a minimum speed requirement is met. If the minimum speed cannot be fulfilled, the port-channel member interfaces are un-programmed and removed from the port-channel, rendering the port-channel functionally inactive, thereby preventing network traffic loss. A timer-based retry sequence attempts to program the constituent interfaces. The minimum speed requirement of the interfaces is checked in the next review cycle. If the minimum speed requirement is met, then the review and retry mechanism halts and the port channel continues to remain active; otherwise, the interfaces are un-programmed and the process repeats.

Review and retry for minimum speed port channel

A review and retry mechanism ensures a port channel can be configured to provide and maintain a minimum data speed. A timer-based review sequence reviews the constituent interfaces of a port channel to determine if a minimum speed requirement is met. If the minimum speed cannot be fulfilled, the port-channel member interfaces are un-programmed and removed from the port-channel, rendering the port-channel functionally inactive, thereby preventing network traffic loss. A timer-based retry sequence attempts to program the constituent interfaces. The minimum speed requirement of the interfaces is checked in the next review cycle. If the minimum speed requirement is met, then the review and retry mechanism halts and the port channel continues to remain active; otherwise, the interfaces are un-programmed and the process repeats.

Dynamically reconfiguring data plane of forwarding element to account for operating temperature
11424983 · 2022-08-23 · ·

Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state.

LOW OVERHEAD ERROR CORRECTION CODE

Memory requests are protected by encoding memory requests to include error correction codes. A subset of bits in a memory request are compared to a pre-defined pattern to determine whether the subset of bits matches a pre-defined pattern, where a match indicates that a compression can be applied to the memory request. The error correction code is generated for the memory request and the memory request is encoded to remove the subset of bits, add the error correction code, and add at least one metadata bit to the memory request to generate a protected version of the memory request, where the at least one metadata bit identifies whether the compression was applied to the memory request.

INSTRUCTION SET ARCHITECTURE WITH PROGRAMMABLE DIRECT MEMORY ACCESS AND EXPANDED FENCE/FLUSH OPERATIONS

In one embodiment, a processor includes decode circuitry and memory offload circuitry. The decode circuitry decodes an instruction to perform a direct memory access (DMA) operation, which includes an opcode and one or more fields. The opcode indicates a type of DMA operation to be performed. The one or more fields indicate a destination memory region and one or more data operands. The memory offload circuitry offloads the instruction from an execution pipeline and performs the DMA operation.

SIMULATING NETWORK FLOW CONTROL

A system simulator simulates operations of a plurality of interconnected devices in a simulation of a computing system. The system simulator implements a communication runtime in the simulation to receive a packet generated by a simulation of a first one of the plurality of devices to be sent to a simulation of a second one of the plurality of devices in the simulation. The communication runtime buffers the packet in its internal buffer and receives a query from the simulation of the second device based on buffer capacity in the simulation of the second device has capacity. The packet is sent from the communication runtime buffer to the simulation of the second device based on the query to simulate transmission of the packet from the first device to the second device on a link.