A network device processes received packets at least to determine port or ports of the network device via which to transmit the packet. The network device also classifies the packets into packet flows, the packet flows being further categorized into traffic pattern categories characteristic of traffic pattern characteristics of the packet flows. The network device buffers, according to the traffic pattern categories of the packet flows, packets that belong to the packet flows in a first packet memory or in a second packet memory, the first packet memory having a memory access bandwidth different from a memory access bandwidth of the second packet memory. After processing the packets, the network device retrieves the packets from the first packet memory or the second packet memory in which the packets are buffered, and forwards the packets to the determined one or more ports for transmission of the packets.

Disclosed is an electronic device including a wireless communication modem, at least one processor connected with the communication modem and comprising a plurality of cores, and a nonvolatile memory operatively connected with the processor, wherein the nonvolatile memory stores instructions that cause a first core of the processor to receive first data packets having a first size from the wireless communication modem, and to transmit at least a portion of the first data packets to a second core of the processor, and that cause the second core to receive the at least a portion of the first data packets from the first core, to merge the at least a portion of the first data packets into a plurality of second data packets having sizes larger than the first size, based at least in part on a type of the first data packets, and to transmit the second data packets to at least one other core of the processor than the first core and the second core.

A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

This disclosure describes systems, methods, and devices related to transmit power control (TPC). A device may identify a link measurement request frame from a first station device. The device may determine, for each transmit chain of the first station device, a TPC action to be performed by the first device. The device may cause to send a link measurement report frame comprising a value indicative of the TPC action for each transmit chain. The device may identify an acknowledgement from the first station device.

A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

Aspects of the invention include receiving an input/output (I/O) request that includes a data stream from a host processor. The receiving is at a network adapter of a storage controller that manages storage for the host processor. The storage controller includes a storage buffer to store data received from the host processor before migrating it to the storage. The storage controller also includes a data cache. It is determined whether the storage buffer has enough free space to store the received data stream. Based at least in part on determining that the storage buffer has enough free space to store the received data stream, the received data stream is stored by the network adapter in the storage. Based at least in part on determining that the storage buffer does not have enough free space to store the received data stream, the received data stream is stored in the data cache.

In some examples, a system on chip (SOC) comprises a network switch configured to receive a packet and to identify a flow identifier (ID) corresponding to a header of the packet. The SOC comprises a direct memory access (DMA) controller coupled to the network switch, where the DMA controller is configured to divide the packet into first and second fragments based on the flow ID and to assign a first hardware queue to the first fragment and a second hardware queue to the second fragment, and wherein the DMA controller is further configured to assign memory regions to the first and second fragments based on the first and second hardware queues. The SOC comprises a snoopy cache configured to store the first fragment to the snoopy cache or to memory based on a first cache allocation command, where the first cache allocation command is based on the memory region assigned to the first fragment, where the snoopy cache is further configured to store the second fragment to the snoopy cache or to memory based on a second cache allocation command, and where the second cache allocation command is based on the memory region assigned to the second fragment.

This disclosure describes systems, methods, and devices related to transmit power control (TPC). A device may identify a link measurement request frame from a first station device. The device may determine, for each transmit chain of the first station device, a TPC action to be performed by the first device. The device may cause to send a link measurement report frame comprising a value indicative of the TPC action for each transmit chain. The device may identify an acknowledgement from the first station device.

A network interface controller (NIC) capable of on-demand paging is provided. The NIC can be equipped with a host interface, an operation logic block, and an address logic block. The host interface can couple the NIC to a host device. The operation logic block can obtain from a remote device, a request for an operation based on a virtual memory address. The address logic block can obtain, from the operation logic block, a request for an address translation for the virtual memory address and issue an address translation request to the host device via the host interface. If the address translation is unsuccessful, the address logic block can send a page request to a processor of the host device via the host interface. The address logic block can then determine that a page has been allocated in response to the page request and reissue the address translation request.

A method of segmented media data processing can include receiving a first sequence of first segments partitioned from a first data stream of a streaming media, and storing the first segments into a first first-in first-out (FIFO) buffer. In the first FIFO buffer, each first segment and attributes associated with each first segment form an entry of the first FIFO buffer. The attributes associated with each first segment can include a start time of the respective first segment, a duration of the respective first segment, and a length of the respective first segment indicating a number of bytes in the respective first segment. The first segments received from the first FIFO buffer can be processed using a first media processing task of a workflow in a network-based media processing (NBMP) system. The first segments received from the first FIFO buffer can be processed independently from each other.