A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.

A network interface device for implementing multi-stream scheduling for time sensitive networking includes direct memory access (DMA) circuitry, comprising: descriptor parsing circuitry to read a packet descriptor from a descriptor cache, wherein the packet descriptor includes at least one scheduling control parameter including: a launch time offset, a gate cycle offset, or a reduction ratio; wherein the packet descriptor is associated with a packet stream having a traffic class; and scheduling circuitry to schedule packets from the packet stream for transmission using the at least one scheduling control parameter.

An implementation may include that a coarse-grained reconfigurable (CGR) processor may be configured to receive a network pause command and to responsively transmit data over the network even though the network pause command is active. The transmission rate may be reduced while the network pause command is active.

The present application relates to devices and components including apparatus, systems, and methods for adjusting a logical channel priority.