A memory of a network device is divided into first blocks, each first block being divided into second blocks, and each second block including a first storage space and second storage space. When a packet is stored, second blocks occupied by the packet are determined based on a packet length and a first storage space length, and the packet is stored into a first storage space of each of the second blocks. For each of the second blocks, a PD corresponding to the second block is generated, and stored into a second storage space of the second block. When a packet is read, the second blocks to be read are determined based on a start address of the packet. A packet fragment is read from a first storage space of the second blocks to be read, and the read packet segments are composed into the second packet to be sent.

Systems, apparatuses, and methods for performing network packet templating for graphics processing unit (GPU)-initiated communication are disclosed. A central processing unit (CPU) creates a network packet according to a template and populates a first subset of fields of the network packet with static data. Next, the CPU stores the network packet in a memory. A GPU initiates execution of a kernel and detects a network communication request within the kernel and prior to the kernel completing execution. Responsive to this determination, the GPU populates a second subset of fields of the network packet with runtime data. Then, the GPU generates a notification that the network packet is ready to be processed. A network interface controller (NIC) processes the network packet using data retrieved from the first subset of fields and from the second subset of fields responsive to detecting the notification.

A traffic manager is shared amongst two or more egress blocks of a network device, thereby allowing traffic management resources to be shared between the egress blocks. Among other aspects, this may reduce power demands and allow a larger amount of buffer memory to be available to a given egress block that may be experiencing high traffic loads. Optionally, the shared traffic manager may be leveraged to reduce the resources required to handle data units on ingress. Rather than buffer the entire unit in the ingress buffers, an arbiter may be configured to buffer only the control portion of the data unit. The payload of the data unit, by contrast, is forwarded directly to the shared traffic manager, where it is placed in the egress buffers. Because the payload is not being buffered in the ingress buffers, the ingress buffer memory may be greatly reduced.

Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

An illustrative embodiment disclosed herein is an object store with distributed caching including a distributed cache cluster including a first cache on a first node device and a second cache on a second node device. The object store with distributed caching further includes a gateway server communicatively coupled to the distributed cache cluster. The gateway server receives a request to store an object from a client device, determines whether the object satisfies an object policy, determines whether the request indicates that the object is to be split up into a plurality of shards, and stores a first shard of the plurality of shards in the first cache and a second shard of the plurality of shards in the second cache.

A transmission device includes N wireless transmission circuits and N transmission buffers. N is an integer equal to or greater than two. Each of the N transmission buffers is connected to a respective wireless transmission circuit of the N wireless transmission circuits. At least a part of a piece of delivery data is stored in each of the N transmission buffers before the N wireless transmission circuits establish wireless links. The N wireless transmission circuits are instructed to transmit the piece of delivery data stored in the N transmission buffers after the N wireless transmission circuits establish the wireless links.

A user traffic generation method includes receiving a user traffic generation instruction, performing, in response to the user traffic generation instruction and index information pre-stored in an on-chip static random access memory (SRAM) of a field programmable gate array, a prefetch operation and a cache operation on a user packet that is stored in a dynamic random access memory DRAM and indicated by the index information, and generating user traffic at a line rate of the user packet that is cached during the cache operation. The on-chip SRAM is configured to store index information of all user packets that need to be used. The DRAM is configured to store all the user packets.

The packet processing system, according to an example embodiment, comprises a Network Interface Controller (NIC) to receive and transmit network packets; a memory unit for storing network packets; a processor for processing network packets stored in the memory unit; a cache unit to access all data to the processor from the memory unit; and an application process running on the processing unit. The NIC includes a packet processing means to process the network packets received by the NIC. The packet processing means includes a Contiguous Header Mapping/Map (CHM) header-data splitter to split said network packets into a header portion and a payload portion; a table or equivalent to store the contiguous header-data split configuration data; and a packet Direct Memory Access (DMA) unit to DMA copy said header portion and said payload portion into separate memory area/location and contiguously map said header portion of network packets in the memory unit.

Some embodiments provide a method for a parser of a processing pipeline. The method receives a packet for processing by a set of match-action stages of the processing pipeline. The method stores packet header field (PHF) values from a first set of PHFs of the packet in a set of data containers. The first set of PHFs are for use by the match-action stages. For a second set of PHFs not used by the match-action stages, the method generates descriptive data that identifies locations of the PHFs of the second set within the packet. The method sends (i) the set of data containers to the match-action stages and (ii) the packet data and the generated descriptive data outside of the match-action stages to a deparser that uses the packet data, generated descriptive data, and the set of data containers as modified by the match-action stages to reconstruct a modified packet.

Systems and Methods for IP and Ethernet switching in an ultra-scalable disaggregated wide area common carrier (WACC) disaggregated networking switching system. The WACC network switching system may include an Ethernet fabric having a set of M Ethernet switches each including a set of N switch ports, and a set of N input/output (IO) devices each including a set of W IO ports, a set of M Ethernet ports, an IO side packet processor (IOSP), and a fabric side packet processor (FSP). Each Ethernet switch may establish switch queues. Each IO device may establish a set of M hierarchical virtual output queues each including a set of N ingress-IOSP queues and ingress-virtual output queues, a set of W egress-IOSP queues, a set of M ingress-FSP queues, and a set of N hierarchical virtual input queues each including a set of N egress-FSP queues and egress-virtual input queues.