In one embodiment, a processor includes decode circuitry and memory offload circuitry. The decode circuitry decodes an instruction to perform a direct memory access (DMA) operation, which includes an opcode and one or more fields. The opcode indicates a type of DMA operation to be performed. The one or more fields indicate a destination memory region and one or more data operands. The memory offload circuitry offloads the instruction from an execution pipeline and performs the DMA operation.

A system simulator simulates operations of a plurality of interconnected devices in a simulation of a computing system. The system simulator implements a communication runtime in the simulation to receive a packet generated by a simulation of a first one of the plurality of devices to be sent to a simulation of a second one of the plurality of devices in the simulation. The communication runtime buffers the packet in its internal buffer and receives a query from the simulation of the second device based on buffer capacity in the simulation of the second device has capacity. The packet is sent from the communication runtime buffer to the simulation of the second device based on the query to simulate transmission of the packet from the first device to the second device on a link.

A system simulator simulates operations of a plurality of interconnected devices in a simulation of a computing system. The system simulator implements a communication runtime in the simulation to receive a packet generated by a simulation of a first one of the plurality of devices to be sent to a simulation of a second one of the plurality of devices in the simulation. The communication runtime buffers the packet in its internal buffer and receives a query from the simulation of the second device based on buffer capacity in the simulation of the second device has capacity. The packet is sent from the communication runtime buffer to the simulation of the second device based on the query to simulate transmission of the packet from the first device to the second device on a link.

A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.

A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.

A switch is provided, which can receive a data communication at an edge of a network. The network may be made up of a plurality of switches. The switch may generate a flow channel based upon an identified source and destination for the data communication. The data communication can be routed across the plurality of switches based on minimizing a number of hops between a subset of the plurality of switches and in accordance with the flow channel.

A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

A network interface controller (NIC) capable of efficient event management is provided. The NIC can be equipped with a host interface, a first memory device, and an event management module. During operation, the host interface can couple the NIC to a host device. The event management module can identify an event associated with an event queue stored in a second memory device of the host device. The event management module can insert, into a buffer, an event notification associated with the event. The buffer can be associated with the event queue and stored in the first memory device. If the buffer has met a release criterion, the event management module can insert, via the host interface, the aggregated event notifications into the event queue.

A network interface controller (NIC) capable of efficient management of non-idempotent operations is provided. The NIC can be equipped with a network interface, storage management logic block, and an operation management logic block. During operation, the network interface can receive a request for an operation from a remote device. The storage management logic block can store, in a local data structure, outcome of operations executed by the NIC. The operation management logic block can determine whether the NIC has previously executed the operation. If the NIC has previously executed the operation, the operation management logic block can obtain an outcome of the operation from the data structure and generate a response comprising the obtained outcome for responding to the request.