A network interface controller (NIC) capable of on-demand paging is provided. The NIC can be equipped with a host interface, an operation logic block, and an address logic block. The host interface can couple the NIC to a host device. The operation logic block can obtain from a remote device, a request for an operation based on a virtual memory address. The address logic block can obtain, from the operation logic block, a request for an address translation for the virtual memory address and issue an address translation request to the host device via the host interface. If the address translation is unsuccessful, the address logic block can send a page request to a processor of the host device via the host interface. The address logic block can then determine that a page has been allocated in response to the page request and reissue the address translation request.

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

In a network interface card, a buffer is provided with a plurality of queues corresponding to packet priority levels, a packet processing circuit stores a packet in a queue in the buffer corresponding to the priority level obtained from a packet received by a physical port, and a control circuit sequentially selects a queue in the buffer on the basis of the packet priority level and allocates a packet read from the selected queue to a computation/processing circuit.

In a network interface card, a buffer is provided with a plurality of queues corresponding to packet priority levels, a packet processing circuit stores a packet in a queue in the buffer corresponding to the priority level obtained from a packet received by a physical port, and a control circuit sequentially selects a queue in the buffer on the basis of the packet priority level and allocates a packet read from the selected queue to a computation/processing circuit.

Techniques are disclosed relating to handling queues. A server-based platform, in some embodiments, accesses queue information that includes performance attributes for a plurality of queues storing one or more messages corresponding to one or more applications. In some embodiments, the platform assigns, based on the performance attributes, a corresponding set of the plurality of queues to each of a plurality of processing nodes of the platform. In some embodiments, the assigning of a corresponding set of queues to a given one of the plurality of processing nodes causes instantiation of: a first set of one or more dequeuing threads and a second set of one or more processing threads. The dequeuing threads may be executable to dequeue one or more messages stored in the corresponding set of queues. The processing threads may be executable to perform one or more tasks specified in the dequeued one or more messages.

A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Embodiments herein describe a group of APs that uses a shared radar cache to select a new channel after vacating a current channel when performing dynamic frequency selection (DFS). The group of APs can set aside memory to store status information about the DFS channels in the frequency band. For example, when one AP detects a radar event (and has to vacate a DFS channel), the AP updates an entry for that channel in the shared radar cache. The APs can also query the cache to determine a new channel after vacating its current channel. That is, the shared radar cache may store the most recent radar events occurring in a channel. In this manner, the APs can select a new channel that has little or no recent radar events, which reduces the likelihood the AP will have to vacate the new channel.

Embodiments herein describe a group of APs that uses a shared radar cache to select a new channel after vacating a current channel when performing dynamic frequency selection (DFS). The group of APs can set aside memory to store status information about the DFS channels in the frequency band. For example, when one AP detects a radar event (and has to vacate a DFS channel), the AP updates an entry for that channel in the shared radar cache. The APs can also query the cache to determine a new channel after vacating its current channel. That is, the shared radar cache may store the most recent radar events occurring in a channel. In this manner, the APs can select a new channel that has little or no recent radar events, which reduces the likelihood the AP will have to vacate the new channel.

One embodiment provides a network interface controller (NIC). The NIC can include a storage device, a network interface, a hardware list-processing engine (LPE), and a message state table (MST) logic block. The storage device can store an MST. The network interface can couple the NIC to a network. The LPE can perform message matching on a first packet of a message received via the network interface. The MST logic block can store results of the message matching in the MST and receive a request to read the results of the message matching from the MST if the NIC receives a second packet associated with the message.