According to an embodiment, a multiplexing device includes: a packet generating unit which generates one or more third packets based on at least one of one or more first packets and a second packet; a main signal generating unit which generates from the third packets a main signal; an information generating unit which generates transmission multiplexing control information; a slot generating unit which generates a slot by combining the transmission multiplexing control information and the main signal corresponding to the information described in the transmission multiplexing control information having been generated a predetermined number of frames prior to the currently generated transmission multiplexing control information; and a time writing unit which writes a time in the second packet in the main signal included in the generated slot.

A method for displaying information and an electronic device, wherein the method includes: receiving a new information; acquiring a level of the new information; acquiring a current state of an information display window; and determining a display mode of the new information for displaying the new information according to the level of the new information and the current state of the information display window, wherein the display mode comprises a direct display mode, a waiting in queue mode and a discarding mode. In the embodiments of the disclosure, levels are assigned to information; after a terminal equipment receives a piece of new information, the terminal equipment will no longer directly display the new information, instead, it will determine a display mode based on the information level and the state of the information display window. Thus, some unimportant information may be filtered off while display of important information is guaranteed, and an overall amount of information to be displayed is reduced; thereby it may be avoided that the display of information occupies many system resources, and the processing load on the terminal equipment may be reduced.

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Example methods and systems for receive side scaling (RSS) are described. In one example, a computer system may generate and send instruction(s) to the programmable physical network interface controller (PNIC) to configure a first flow entry that associates a first packet flow with a first queue and a second flow entry that associates a second packet flow with a second queue. In response to receiving a first packet that is associated with the first packet flow, the programmable PNIC may match the first packet with the first flow entry and steer the first packet towards the first queue for processing by a first processing thread. In response to receiving a second packet that is associated with the second packet flow, the programmable PNIC may match the second packet with the second flow entry and steer the second packet towards the second queue for processing by a second processing thread.

There is provided a communication control apparatus comprising a processor. The processor receives, from a first mobile communication apparatus, a request for permission of data transmission to a second mobile communication apparatus, the second mobile communication apparatus including a buffer memory to store received data. The processor determines whether to permit the data transmission based on a free capacity of the buffer memory and a reserved capacity indicated by a reservation setting of the buffer memory. The processor updates, when the data transmission is determined to be permitted, the reservation setting such that a capacity for received data corresponding to the data transmission is added to the reserved capacity. The processor transmits, when the data transmission is determined to be permitted, a response indicating that the data transmission is permitted to the first mobile communication apparatus.

There is provided a communication control apparatus comprising a processor. The processor receives, from a first mobile communication apparatus, a request for permission of data transmission to a second mobile communication apparatus, the second mobile communication apparatus including a buffer memory to store received data. The processor determines whether to permit the data transmission based on a free capacity of the buffer memory and a reserved capacity indicated by a reservation setting of the buffer memory. The processor updates, when the data transmission is determined to be permitted, the reservation setting such that a capacity for received data corresponding to the data transmission is added to the reserved capacity. The processor transmits, when the data transmission is determined to be permitted, a response indicating that the data transmission is permitted to the first mobile communication apparatus.

A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.

In a method for queuing data units in a network device, a plurality of physical queues corresponding to a port of the network device are defined in a memory of the network device. Respective subsets of the plurality of physical queues are logically coupled to define a plurality of logical queues that are respectively formed of logically coupled physical queues. The logical queues correspond to respective data flows of the port. A data unit belonging to a data flow is received. A logical queue for storing the data unit is selected, based on the data flow of the data unit, from the plurality of logical queues The A physical queue for storing the data unit is then selected from the subset of physical queues that corresponds to the selected logical queue. The data unit is stored in the selected physical queue.

A system for adaptive audio video (AV) stream processing may include at least one processor and a switch device. The switch device may be configured to route AV traffic to the processor, and to receive AV traffic from the processor and provide the AV traffic to a client device via one or more channels. The processor may monitor a transcoder buffer depth and depths of buffers associated with channels over which the AV traffic is being transmitted. The processor may adaptively modify one or more attributes associated with the AV traffic based at least on the monitored buffer depths. For example, the processor may adaptively adjust a bit rate associated with transcoding the AV traffic based at least on the transcoder buffer depth. The processor may utilize the depths of the buffers associated with the channels to adaptively adjust the amount of AV traffic provided for transmission over the channels.