A switch equipped with a reduction engine capable of being dynamically allocated in a network is provided. During operation, the reduction engine can be dynamically armed based on a multicast frame. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

An apparatus of a communication device, the apparatus may include: a memory; and a processor configured to: receive a plurality of data packets at a layer of a network protocol stack;

determine a result, wherein the result represents whether a data packet of the plurality of data packets belongs to an application client; provide instructions to cause the memory to store the data packet within either a first buffer or a second buffer based on the result; and process, at the layer of the network protocol stack, the plurality of data packets stored in the first buffer and the second buffer.

An apparatus of a communication device, the apparatus may include: a memory; and a processor configured to: receive a plurality of data packets at a layer of a network protocol stack;

determine a result, wherein the result represents whether a data packet of the plurality of data packets belongs to an application client; provide instructions to cause the memory to store the data packet within either a first buffer or a second buffer based on the result; and process, at the layer of the network protocol stack, the plurality of data packets stored in the first buffer and the second buffer.

A storage system includes a plurality of storage controllers. The storage controller includes a processor, a memory, and a transfer device that processes control data for controlling an internal operation of the storage system, the control data being transmitted and received between the plurality of storage controllers. The processor accumulates the control data in the memory when a transfer request for the control data is generated, generates a write request for transmitting a plurality of the control data stored in the memory, and transmits the write request to the other storage controller. The transfer device writes a plurality of the control data included in the write request to the memory upon receiving the write request.

A storage system includes a plurality of storage controllers. The storage controller includes a processor, a memory, and a transfer device that processes control data for controlling an internal operation of the storage system, the control data being transmitted and received between the plurality of storage controllers. The processor accumulates the control data in the memory when a transfer request for the control data is generated, generates a write request for transmitting a plurality of the control data stored in the memory, and transmits the write request to the other storage controller. The transfer device writes a plurality of the control data included in the write request to the memory upon receiving the write request.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

Methods and systems are provided for controlling wide LAG and ECMP in a network. At the ingress edge of the network, a switch can identify packets as LAG or ECMP packets, and allow them to be forwarded through the switch fabric using multiple output ports or paths.

Methods and systems are provided for controlling wide LAG and ECMP in a network. At the ingress edge of the network, a switch can identify packets as LAG or ECMP packets, and allow them to be forwarded through the switch fabric using multiple output ports or paths.

Systems and methods for dynamic buffer management in switches that facilitate a data-driven intelligent networking system are provided. The system can accommodate dynamic traffic with fast, effective congestion control while providing efficient use of internal input buffer space.